Using SDRAM on Xilinx AFX V2P board

The following is the snippet of C code to test SDRAM connected to OPB from MEMEC design resources.

// Type casting unsigned int* sdram_location = (unsigned int *) XPAR_SDRAM1_BASEADDR; int sdram_data_read, sdram_data_read_error; unsigned int* temp;

//Store values temp = sdram_location; for (loop_count = 0; loop_count < 4194304; loop_count++) { *sdram_location = loop_count; sdram_location++; }

//Retrieve values sdram_location = temp; for (loop_count = 0; loop_count < 4194304; loop_count++) { sdram_data_read = *sdram_location;

if (sdram_data_read != loop_count) { printf_uart(" SDRAM Test Failed\n\r"); loop_count = 4194305; } else { sdram_location++; } }

hope this helps Ram

Thanks for the reply, but what I was really after was advice relating to the design I've implemented. I'd already implemented my own code to verify that either the SDRAM was failing or my design wasn't using the SDRAM connectly. What I'm trying to understand if *why* the SDRAM isn't working, despite having done everything the documentation suggests (to the best of my knowledge).

The design practically left everything up to the base system builder, and the only thing I did was correct the pin definitions in the UCF board, and ensure that I was using the correct oscillator socket, and that the DRAM enable pin was set corrently.

I'm told that SDRAM chips are very sensitive to the clock they're given, and that if it says it is to be clocked at a specific frequency it really means that. I failed to find appropriate documentation for the SDRAM chip on the AFX board we have - the URL in the board documentation is no longer valid, and searching the web site the for the makings on the chip (1QE42 ZVCGC) didn't turn up anything either.

Whoever wrote this code needs to be introduced to the C keyword "break" :)

Cheers,

Hi Michael,

I've just sent the manual of the SDRAM chip on the AFX V2P board to your email snipped-for-privacy@thompson.cl.cam.ac.uk Hope that you can receive it (it's about 1.7M : )

Cheers, Tyrone

"Michael Dales" ??? news: snipped-for-privacy@thomps>

"Tyrone Kwok" writes:

Many thanks Tyrone.

I've checked all the parameters I was giving the SDRAM core to the document, and still I'm not having any luck. Below is the parameters I use, taken from the system.mhs file in EDK:

# Confirmed that we have a -8 grade part (engineering sample) (ZVCGC) BEGIN opb_sdram PARAMETER INSTANCE = SDRAM_8Mx32 PARAMETER HW_VER = 1.00.d PARAMETER C_INCLUDE_HIGHSPEED_PIPE = 0 PARAMETER C_SDRAM_TCCD = 1 # confirmed (cas - 1 for read, any clock for write) PARAMETER C_SDRAM_TRAS = 48000 # confirmed (48 for -8, 50 for -10) PARAMETER C_SDRAM_TRC = 80000 # confrimed (80 for -8, 100 for -10) PARAMETER C_SDRAM_TRFC = 80000 # confirmed (80 for -8, 100 for -10) PARAMETER C_SDRAM_TRCD = 20000 # confirmed PARAMETER C_SDRAM_TRRD = 20000 # confirmed PARAMETER C_SDRAM_TRP = 20000 # confirmed PARAMETER C_SDRAM_TREF = 64 # confirmed (4096 refreshes every 64 ms) PARAMETER C_SDRAM_REFRESH_NUMROWS = 4096 # confirmed PARAMETER C_SDRAM_CAS_LAT = 2 # confirmed (2 for -8, 3 for -10) PARAMETER C_SDRAM_COL_AWIDTH = 8 # confirmed PARAMETER C_SDRAM_BANK_AWIDTH = 2 # confirmed PARAMETER C_SDRAM_AWIDTH = 11 # confirmed PARAMETER C_SDRAM_DWIDTH = 32 # confirmed PARAMETER C_SDRAM_TWR = 15000 # confirmed PARAMETER C_SDRAM_TMRD = 2 # confirmed PARAMETER C_OPB_CLK_PERIOD_PS = 10000 # confirmed PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x007fffff BUS_INTERFACE SOPB = opb PORT OPB_Clk = sys_clk_s PORT SDRAM_CLK_in = sys_clk_s PORT SDRAM_WEn = SDRAM_8Mx32_SDRAM_WEn PORT SDRAM_CKE = SDRAM_8Mx32_SDRAM_CKE PORT SDRAM_CASn = SDRAM_8Mx32_SDRAM_CASn PORT SDRAM_RASn = SDRAM_8Mx32_SDRAM_RASn PORT SDRAM_Addr = SDRAM_8Mx32_SDRAM_Addr PORT SDRAM_DQ = SDRAM_8Mx32_SDRAM_DQ PORT SDRAM_DQM = SDRAM_8Mx32_SDRAM_DQM PORT SDRAM_BankAddr = SDRAM_8Mx32_SDRAM_BankAddr END

Does this match what you've got set for the SDRAM?

Cheers,

Hi,

The SDRAM chip on my board is DVCGC, which is also a -8 grade part. BTW, I find one discrepancy with your parameters:

My value for this is 17000, 1tCK + 7 ns. Please refer to P.33 of the manual.

BTW, I've just written a simple program which writes to and then reads from a single address, and it reads correctly.

Cheers, Tyrone

"Michael Dales" ???????: snipped-for-privacy@thomps>

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