Hi all,
I'm making a system on iCE40 and I've ran out of PLLs. The design incorporates two DDR2 controllers that need to perform several operations delayed with respect to the system clock. I'm gonna use a phase delayed clock for that.
So my approach is to take the clock signal and pipe it through several LUTs, thus delaying it.
But - how comparable are LUT delays between different chips? As in, different pieces of FPGA silicon? If I implement this design, will every chip be a special snowflake that needs to be calibrated separately and use different lengths of LUT delay gates?