Hello, I'm trying to implement a bidirectional bus. I've declared the port as inout std_logic_vector, and the simulation shows only "UUU...". Any idea how I control the inout bus?
read: process(clk2x) begin if rising_edge(clk2x) then if read_data = '1' then u_data_o
********** Are you sure you meant 'read_data' there? Else it only tristates when you're not reading. I think. HTH, Syms. **********
The inout buses are controlled in the same manner as in or out buses Make sure that the ddr_dq and u_data_i are getting values at the previous edge of when u expects the data in the inout bus.
Put the data busses out of the process. Write it as a concurren statement and use one output_enable(OE) signal to control the inou bus
inout_bus 'Z')
in_bus
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