To interface a fast sampling ADC to a CPU I'm considering to use a fifo or dual ported ram and a small controlling CPLD. Cypress has a nice offering of fifos and dp-rams, but looking at the prices of 512kb density parts I got a bit of a shock: $75 for the fifo and $45 for the dp-ram. That's in single quantity, but they don't go down fast either: $30/1000+ for the dp-ram. :-( (prices from cypress website)
For less money, you can have a Xilinx spartan-6 (XC6SLX9-2TQG144C $20/1+ $14/1000+) with 512kB of Block ram. And you get your controlling 'CPLD' for free. OK you still need a config memory. (prices from avnet website)
Can you just connect one side of the block ram to IO pins and read that from a CPU as if it where a dp-ram? Other side interface would even be simpler as you can keep it internal.
Am I missing something here or is it really that simple? (And yes, I do realize I have to program the FPGA to perform the required function ;-) )
Sample rate is not extremely high (10MSPS), but too fast for the CPU to read on interrupts directly. There may be other options, still investigating.