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Using BUFG with internally generated clocks

I'm trying to use a Xilinx XC2VP20 (Virtex II Pro family) to prototype an ASIC device but I'm experiencing a lot of trouble cause i'm new to FPGA. The problem is that my project has various asyncronous clocks generated internally by means of dividers and NCOs. I would like to route these clocks through low skew lines by instantiating BUFG blocks (I've read on the Virtex II Pro user guide that it is possible) but even if XST compiles without errors ISE is not able to translate the design. Does anyone knows if I'm trying the impossible or has any suggestion? Any help will be strongly appreciated...

Reply to
Di Pascale
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Hi, Check the availability of BUFG's in your device(do you exceed?). There are some other options like taking the clk to I/O pin and bringing back the clk and using a DLL to adjust the skew as required(which is best option i think, with assumption that you have spare I/O pins and DLL's available in your device).

Thanks rao

Reply to
pablo

No, I'm using only 4 out of 16 BUFG available.

I'd like to change the original VHDL the less I can (you know, the aim is to validate it, not just obtaining a working design...) but it seems a good idea and I think I'll try it out if I can't find anything less invasive, thanks a lot.

Reply to
Di Pascale

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