Using 3.3V compliant FPGA for 5V PCI

Hello,

I have to design a universal PCI card according to PCI spec 2.2 with

33Mhz and 32 pins. However for several reasons I have to use a FPGA that is not 5V but only 3.3V tolerant. Since nearly all motherboards just offer 5V slots I have to make this card somehow 5V compliant. I thought of using a quickswith from IDT. Is this a good idea? What are the things I have to take care of when using this method? Are there any other ways to make my card 5V compliant?

thanks+regards, Nicky

Reply to
Nicky
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Nicky, do a google groups search on this newsgroup for some discussions on this.

My Cyclone PCI board (details on web site) uses Quickswitches and appears to work flawlessly.

This approach isn't actually compliant with the PCI spec which stipulates 1 load per net, but I met the capacitance limits and inspection shows clean transitions on the bus.

Hope this helps,

Nial

------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design

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Reply to
Nial Stewart

Hi,

I recommend you take a look at Xilinx application note 646

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Sim>Hello,

Reply to
Simon Tam

Thank you for your answer. In the meanwhile I already read all the threads I could find in this newsgroup concerning this topic.

Your PCI-card is a universal card as well. In a 5V PCI slot the Quickswithes transfer 5V to 3.3V in one direction and the other way round in the other direction but what does the Quickswith do in a 3.3V slot?

And I have another question. Somewhere in a newsgroup message I read that for universal PCI cards it is necessary to store 2 different bitfiles in an EEPROM and configure the PCI-FPGA depending on the voltage. That is to say 3.3V needs another configuration than 5V. Is this true? If yes, why? Anyway I can't do that since I use a Lattice FPGA which provides an internal EEPROM and my board is not going to have an external one additionally.

I planed to use the PCI clock and put it into a PLL in the PCI-Core Lattice and consequently distribute the PLL-generated clock to other devices on my PCI card. I read that on your board the PCI-Clk is also routed to a PLL and is available for user logic. However, I read that this is maybe not a good idea since according to the PCI-spec it is possible that the PCI-clk is 0-33 MHz. On the other hand with an external oscillator there are much more problems with synchonisation. How did you tread this problems? Does the Altera Cyclone provide intern FIFOs with 2 different clocks?

I hope you can help me again + best regards

Reply to
Nicky

In a 3.3 volt slot the quick switch conducts without affecting the signal appreciably. A 5 volt signal is limited (clipped) by the Vcc to the switch. The switch is not really doing a voltage translation. It just raises its resistance significantly when the signal voltage gets near Vcc.

The difference between the two standards is not just voltage levels. The 3.3 volt bus *requires* internal diodes to Vcc to limit overshoot. On a 5 volt bus these would cause real problems since signals can swing above 3.3 volts normally. But if you are using the quick switches, the FPGA will not see the voltages above 3.3 volts no mater what the bus does. So you can live with one FPGA load. I am not sure how the quick switches perform compared to the spec. The fact that your card seems to work in a small system does not mean you are meeting spec or that it will work in a heavily loaded system.

I don't know if the PLL inside the FPGA will do a good job of distributing this signal. This will require feedback from the output pin to align the output to the clock input. Standard clock chips will do a much better job of this.

You will not find many PCI implementations that run the clock much below

33 MHz. But you will find some that jitter it to spread the EMI across a wider spectrum and lower the readings. I believe this is not extensive and is compatible with most PLLs, but you should verify this.
--
Rick "rickman" Collins

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Reply to
rickman

Rick wrote -

The PLLs in the Lattice device have selectable internal or external feedback, which will allow you to null out board level delays effectively. Works quite well.

Michael Thomas LSC SFAE New York/New Jersey

631-874-4968 fax 631-874-4977 snipped-for-privacy@latticesemi.com for the latest info on Lattice products -
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LATTICE - BRINGING THE BEST TOGETHER
Reply to
Mikeandmax

It's important to note that the Quick switch must run on 5 volts in either case, not at Vio. Internally the quick switch FETs need about a volt and a half above the highest required output drive voltage.

Reply to
Gabor Szakacs

Actually, I think they need to run off a separate IO voltage. I belive there is an app note on one of the manufacturer's web sites showing that a diode drop is useful to provide this voltage from 5.0 volts.

--
Rick "rickman" Collins

rick.collins@XYarius.com
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Reply to
rickman

Altera has published AN330: Connecting Altera 3.3-V PCI Devices to a

5-V PCI Bus. This AN describes the technique of using an IDT Quickswitch, and also addresses devices from TI, Pericom, and Fairchild. We have used this technique on the Stratix PCI Development Board to implement a universal (3.3V/5.0V) board. Not strictly compliant due to the added capacitance, but it works.

You can find the AN here:

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You can find info on the PCI Dev Kit board here:

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This info includes details on how the QuickSwitches were wired up.

Sincerely, Greg Steinke snipped-for-privacy@altera.com Altera Corporation

Reply to
Greg Steinke

Hello,

read the solution under

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It is also 3,3 and 5V with a Spartan-IIE.

"Nicky" schrieb im Newsbeitrag news: snipped-for-privacy@posting.google.com...

Reply to
Torsten Lauter

Specifically, which FPGA?

Assuming you are designing a product, get the PCI specification, and make sure your circuitry to convert from one signaling level to the other doesn't violate it. I don't have it handy right now but if you're an engineer designing a PCI card you really should have it. If this is for a one or two of a kind board (not a product), you can cheat or hack as you wish.

Loading, trace lengths, capacitence.

Reply to
William Wallace

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