User masks in HardCopy and HardCopy II

Shyam,

HardCopy II uses two layers of metal customization, plus three via layers as well, for a total of 5 masks. The layers altered are in the middle of the metal stack (actually metal layers 5 and 6). With HardCopy Stratix we used a similar arrangement but on a 130nm rather than 90nm process of course.

The turnaround time we are quoting for both HardCopy Stratix and HardCopy II is approximately the same (to a limited extent it is design dependent, and this can affect what you get quoted). By Q4 of this year, the turnaround time of HardCopy II will be lower than HC Stratix. This is for two reasons. Firstly the flow for HC II has been designed with increased automation in mind, and we are ramping this up as we do more designs. Secondly, the logic fabric of HC II allows for much higher performance in comparison with the initial FPGA than HC-Stratix did. This gives us more margin in meeting timing and means it's much easier to get timing closure when doing final routing of the HC II device. This is going to translate into shorter conversion times.

Hope this helps.

Paul.

Shyam wrote:

Carefull, if customers hear that, you know what they are going to ask a) Can we please have the faster speed, sir ? b) Since this is such a doddle, the NRE costs will plumet too, right ?

Only the unreasonable ones would expect both at the same time.. :)

-jg

Thanks a lot Paul. Sure helps. But gives rise to a couple more technical questions in my mind that I hope you'll be able to clarify.

My understanding is that HardCopy II makes use of fine-grained architecture blocks known as HCells. Precharacterized HCell macros form a library of various Stratix II ALM and DSP block configurations. If my understanding is correct,looks like two kinds of customizations would be required in HardCopy II: one, customization within each HCell macro and two, customization to route together all HCell macros/memory blocks. Here are my questions:

1. Are the fine-grained structures within a HCell macro interconnected using layers like via4/metal5/via5/metal6/via6? Does this potentially give rise to any electrical reliability issues because perhaps a lot of vias (via4 on via3 on via2 on via1) need to be stacked to form even local connections (say between fine-grained structures like NAND gates, inverters, transistors etc.)?

1. Is the MultiTrack routing architecture of Stratix II (R4/R24/C4/C16 etc.) preserved in HardCopy II? Is the global routing (between HCell macros/memory blocks) carried out using customer metal layers 5 and 6?

2. Can using only two metal layers for both local routing (within HCell macros) and global routing (between HCell macros/memory blocks) routing cause problems during migration because of congestion issues? Can the migration be unsuccessful for certain designs?

I understand that in raising the above questions I am making certain assumptions regarding HarCopy II implementation which may not be correct and I apologize for that. Any clarification would be very helpful. Thanks again.