I like to simulate our design by using Xilinx library elements (RAMB16_s4_s4) with ModelSim SE plus 5.7d (on PC). While using the downloaded xilinx_lib_4.tcl file I obtain the following error messages:
# Model Technology ModelSim SE vcom 5.7d Compiler 2003.05 May 10 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package vital_timing # -- Loading package vital_primitives # -- Loading package textio # -- Compiling package vpackage # -- Compiling package body vpackage # -- Loading package vpackage # Model Technology ModelSim SE vcom 5.7d Compiler 2003.05 May 10 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package vital_timing # -- Compiling package vcomponents # Model Technology ModelSim SE vcom 5.7d Compiler 2003.05 May 10 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package vital_timing # -- Loading package vital_primitives # -- Loading package textio # -- Loading package vpackage # -- Compiling entity x_and16 # -- Compiling architecture x_and16_v of x_and16 # -- Compiling entity x_and2 # -- Compiling architecture x_and2_v of x_and2 # -- Compiling entity x_and3 # -- Compiling architecture x_and3_v of x_and3 # -- Compiling entity x_and32 # -- Compiling architecture x_and32_v of x_and32 # -- Compiling entity x_and4 # -- Compiling architecture x_and4_v of x_and4 # -- Compiling entity x_and5 # -- Compiling architecture x_and5_v of x_and5 # -- Compiling entity x_and6 # -- Compiling architecture x_and6_v of x_and6 # -- Compiling entity x_and7 # -- Compiling architecture x_and7_v of x_and7 # -- Compiling entity x_and8 # -- Compiling architecture x_and8_v of x_and8 # -- Compiling entity x_and9 # -- Compiling architecture x_and9_v of x_and9 # -- Compiling entity x_bpad # -- Compiling architecture x_bpad_v of x_bpad # -- Compiling entity x_buf # -- Compiling architecture x_buf_v of x_buf # -- Compiling entity x_buf_pp # -- Compiling architecture x_buf_pp_v of x_buf_pp # -- Compiling entity x_bufgmux # -- Compiling architecture x_bufgmux_v of x_bufgmux # -- Compiling entity x_bufgmux_1 # -- Compiling architecture x_bufgmux_1_v of x_bufgmux_1 # -- Compiling entity x_ckbuf # -- Compiling architecture x_ckbuf_v of x_ckbuf # -- Compiling entity x_clkdll_maximum_period_check # -- Compiling architecture x_clkdll_maximum_period_check_v of x_clkdll_maximum_period_check # -- Compiling entity x_clkdll # -- Compiling architecture x_clkdll_v of x_clkdll # -- Loading entity x_clkdll_maximum_period_check # -- Compiling entity x_clkdlle_maximum_period_check # -- Compiling architecture x_clkdlle_maximum_period_check_v of x_clkdlle_maximum_period_check # -- Compiling entity x_clkdlle # -- Compiling architecture x_clkdlle_v of x_clkdlle # -- Loading entity x_clkdlle_maximum_period_check # -- Compiling entity dcm_clock_divide_by_2 # -- Compiling architecture dcm_clock_divide_by_2_v of dcm_clock_divide_by_2 # -- Compiling entity dcm_maximum_period_check # -- Compiling architecture dcm_maximum_period_check_v of dcm_maximum_period_check # -- Compiling entity dcm_clock_lost # -- Compiling architecture dcm_clock_lost_v of dcm_clock_lost # -- Compiling entity x_dcm # -- Compiling architecture x_dcm_v of x_dcm # -- Loading entity dcm_clock_divide_by_2 # -- Loading entity dcm_maximum_period_check # -- Loading entity dcm_clock_lost # -- Compiling entity x_fddrcpe # -- Compiling architecture x_fddrcpe_v of x_fddrcpe # -- Compiling entity x_fddrrse # -- Compiling architecture x_fddrrse_v of x_fddrrse # -- Compiling entity x_ff # -- Compiling architecture x_ff_v of x_ff # -- Compiling entity x_ibufds # -- Compiling architecture x_ibufds_v of x_ibufds # -- Compiling entity x_inv # -- Compiling architecture x_inv_v of x_inv # -- Compiling entity x_ipad # -- Compiling architecture x_ipad_v of x_ipad # -- Compiling entity x_keeper # -- Compiling architecture x_keeper_v of x_keeper # -- Compiling entity x_latch # -- Compiling architecture x_latch_v of x_latch # -- Compiling entity x_latche # -- Compiling architecture x_latche_v of x_latche # -- Compiling entity x_lut2 # -- Compiling architecture x_lut2_v of x_lut2 # -- Compiling entity x_lut3 # -- Compiling architecture x_lut3_v of x_lut3 # -- Compiling entity x_lut4 # -- Compiling architecture x_lut4_v of x_lut4 # -- Compiling entity x_lut5 # -- Compiling architecture x_lut5_v of x_lut5 # -- Compiling entity x_lut6 # -- Compiling architecture x_lut6_v of x_lut6 # -- Compiling entity x_lut7 # -- Compiling architecture x_lut7_v of x_lut7 # -- Compiling entity x_lut8 # -- Compiling architecture x_lut8_v of x_lut8 # -- Compiling entity x_mult18x18 # -- Compiling architecture x_mult18x18_v of x_mult18x18 # -- Compiling entity x_mult18x18s # ** Error: C:/Programme/FPGAdv61/Modeltech/xilinx/vhdl/unisim/ramb4_s16_s16/vhdl/src/simpri ms/simprim_VITAL.vhd(9368): VITAL TISD timing generic must be a scalar form of VITAL # delay type # (1076.4 section 4.3.2.1.3.13) # ** Error: C:/Programme/FPGAdv61/Modeltech/xilinx/vhdl/unisim/ramb4_s16_s16/vhdl/src/simpri ms/simprim_VITAL.vhd(9369): VITAL TISD timing generic must be a scalar form of VITAL # delay type # (1076.4 section 4.3.2.1.3.13) # ** Error: C:/Programme/FPGAdv61/Modeltech/xilinx/vhdl/unisim/ramb4_s16_s16/vhdl/src/simpri ms/simprim_VITAL.vhd(9391): VHDL Compiler exiting
What can I do/where can I obtain already compiled Xilinx library elements for simulation ?
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