Hi,
I am trying to make a multi core processor design on board of virtex 4 family. I have 2 processors so i believe that I would need 2 local memory units, that is two BRAM blocks. One for each of the processor.
What is happening is when i am synthesizing the design I find that I am using more number of RAMB16 primitives than what are there on the board. I am using 52 while there are just 36 on the board.
I am using Xilinx Platform Studio for this purpose. It computes the BRAM block size, Address Width and Data Width on it's own. I am not sure if there is some way I can configure this.
Please tell me how I can reduce the number of RAMB16 primitives that I am using.
Thanks in Advance,
Bhanu
P.S: Board I am using is ML403 board.