I am using the ML401 board to build up some test logic. The 100MHz XO on the baord is fed into a DCM via a global buffer. I am using the FX output (x3) to bump the clock up to 300MHz. There is no feedback source on this DCM b/c I don't care about its input/output phase relationship. That FX output is fed to another DCM. The CLK0, CLK90, CLK180, CLK270, and CLKDIV outputs are all used.
I am using a data generator to input an LVDS signal. The two signals (data_p and data_n) are fed into the FPGA and connected to an instantiated differential buffer with an LVDS_25 attibute. The output of the buffer is fed to both an external IO and internal logic. I just want to check to make sure the LVDS signal is being transmitted and buffered correctly.
I am scoping the output IO (buffered LVDS - single-ended signal at this point) and see some odd behavior. With the LVDS signal ON, the output of the pin looks good. It is the single-ended data I would expect. However, if I turn the data generator off, I get a 300 MHz clock on the output. It is at the IO voltage too - 2.5V...and clean! Now, I can turn the OUTPUT channels of the data generator off. That removes the DC bias on the data_p and data_n signals. The output on the IO pin at that point is garbage...no signal, but it is ugly...not 0 output.
If I reset the board...really just resets the DCM and internal logic of the FPGA, the output IO is a 100MHz clock! Remember, this is with the data generator output channels OFF. If I turn them ON (channles are DC biased but no activity on them) and THEN reset the board, I will get the 300MHz clock output. The weird thing is, is that I can HOLD the reset to the board and the 300MHz clock never goes away! I would think that the reset to the DCM's would disable all clock signals. I have checked the data generator to make sure that it wasn't introducing a rogue clock. It isn't. I have moved its output frequency around and never seen it on the output.
I really haven't looked into this much, but wanted to throw it out here to see if I am missing something obvious.
Thanks.