Hi all ... I have been writing VHDL for many years now, but can't seem to figure something out. I'm writing a component called "cell" (no it has nothing to do with the cell processor). Since there are so many different variations on my cell architecture I have chosen to use generics and generate statements to create the necessary cell type based on generic values.
Notice below that I have an input ep_in. Well, on some cells I don't need that input because the number of eprobs is zero. However, if I set num_eprobs to 0, ep_in becomes std_logic_vector(-1 downto 0).
Is there some way to disable the ep_in port when num_eprobs is 0? If not, does anyone have any clever ideas on how to get around this?
Thanks, James
entity cell is generic (cell_type : cell_types; num_children : integer range 1 to 6; num_eprobs : integer range 0 to 16; precision : integer); port ( clk : in std_logic; reset_l : in std_logic; -- c_in : in std_logic_vector(num_children*precision-1 downto 0); tp_in : in std_logic_vector(num_children*precision-1 downto 0); ep_in : in std_logic_vector(num_eprobs*precision-1 downto 0); -- val : out std_logic_vector(precision-1 downto 0)); -- output end cell;