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Unpicking Logical Synthesis

Hiya group,

I've got a design that is contained within a single VHDL file. It instantiates a component that is in an NGC format, so I have two files in my ISE project, one VHDL and one NGC. What I would like to be able to do is synthesise both to a single NGC by passing through the logical synthesis stage in ISE (XST). I'd like to get the estimated combined resource use and clock rate this way, and have a single logical netlist for the design to export it. Is there any easy way to do this?

== tin-foil hat on == Is there anyway to return to VHDL from the NGC stage (even via EDIF)? == tin-foil hat off ==

Thanks,

Robin

Reply to
Robin Bruce
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There is an ngc2edif tool shipped with ISE. I think I've walked this route once to turn an ngc into a vhdl file.

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Reply to nico@nctdevpuntnl (punt=.)
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Reply to
Nico Coesel

Thanks Nico,

I thought the ngc2edif tool might come into it somewhere, but how exactly do I end up with a VHDL file?

Cheers,

Rob> "Rob>

Reply to
Robin Bruce

Mentor tools such as Leonardo or Precision can take an EDIF and produce a VHDL file - it's not terribly readable, but you can simulate it. I am sure the other vendors can do the same trick. /Mike

Reply to
MikeJ

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