dear
i am using 'unisim' for Xilinx component for VHDL "simulation" in Modelim. So, as far we know the name of the component, no VHDL description (implementation) was required, which was convenient.
Now I am wondering whether it is possible to
- synthesize Xilinx component uing unisim only,
Should I use 'coregenerator' to synthesize?
Thankyou in advance