NET "cp100" TNM_NET = "cp100"; TIMESPEC "TS_cp100" = PERIOD "cp100" 10 ns HIGH 50 % INPUT_JITTER 400 ps; TIMEGRP "cp100anxffs" = FALLING FFS; TIMEGRP "cp100axffs" = RISING FFS;
TIMEGRP "TG_S1S2D_INPADS" = PADS( "s1d" "s1d" "s1d" "s1d" "s1d" "s1d" "s1d" "s1d" "s2d" "s2d" "s2d" "s2d" "s2d" "s2d" "s2d" "s2d" );
TIMEGRP "TG_S1S2D_INPADS" OFFSET = IN -3 ns VALID 5 BEFORE "cp100" TIMEGRP "cp100anxffs" ;
I'm using a virtex2 part with a differential 100mhz lvpecl clock. s1d(x) and s2d(x) go directly into FFs clocked on the falling edge of the 100mhz clock. The data at the s1d(x) and s2d(x) input pads are valid 2ns before the falling edge and 3 ns after. Are my constraints setup correctly above? I'm confused because I'm using the falling edge of the 100mhz clock. And I am getting hold errors when I run the Timing Analyzer with -min times but not with -4 times. Any and all comments appreciated. Thanks.