While compliling my VHDL design with XILINX ISE, I received the following error concerning a IO-constraint:
Annotating constraints to design from file "noc_top.ucf" ... ERROR:NgdBuild:755 - Line 7 in 'noc_top.ucf': Could not find net(s) 'lclk' in the design. To suppress this error specify the correct net name or remove the constraint. The 'Ignore I\O constraints on Invalid Object Names' property can also be set ( -aul switch for command line users). ERROR:Parsers:11 - Encountered unrecognized constraint while parsing. ERROR:NgdBuild:19 - Errors found while parsing constraint file "noc_top.ucf".
In the design top level file, lclk is an input port.
Entity of TOP-LEVEL-VHDL-File: entity noc_top is port( lclk : in std_logic; boardout : out std_logic_vector(6 downto 0); anode : out std_logic); end noc_top;
Corresponding UCF-File ########################################################## NET "lclk" LOC=3D"T9"; NET "boardout" LOC=3D"E13"; NET "boardout"
If I change the port name simultaneously in the design file and in the ucf, the error is still indicated.
Does is depend on the port direction (all output port are mapped correctly) ?
Any ideas ??? J=FCrgen