Hello,
I'm trying to learn VHDL and here I'm adding a parity bit to Ben Cohen's UART Receiver. RxReg(9) is incoming parity bit from transmitter side. A 0 output at Parity_err means no parity error detected and otherwise. The receiver has to match the incoming parity bit with its own parity bit which is calculated using XOR of its data byte, RxReg(8 downto 0). My statement below is giving me a full byte delay because my control statements for the parity check. I think it's because of the process statement, but that's all I can think of now.
can someone let me know how to fix this?
Thanks, AS
------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL;
-------------------------------------------------------------------------------
--
-- Project : ATEP
-- File name : uartrx.vhd
-- Title : UART Receiver
-- Description : UART receiver selection
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Author Revision Comments
-- Sat Oct 30 10:05:49 1994 cohen Rev A Creation
------------------------------------------------------------------------------- entity UartRx_Nty is port (Clk16xT : in std_logic; -- 16 of these clocks per bit ResetF : in std_logic; Serial_InT : in std_logic; DataRdyT : out boolean; DataOuT : out std_logic_Vector(7 downto 0); Parity_err : out std_logic; -- Parity Error Output BitClkT : out std_logic); -- same speed clock as Tx end UartRx_Nty;
architecture UartRx_Beh of UartRx_Nty is subtype Int0to15_Typ is integer range 0 to 15; constant RxInit_c : std_logic_Vector(10 downto 0) := "11111111111"; signal RxReg_s : std_logic_Vector(10 downto 0); -- the receive register signal Count16_s : Int0to15_Typ; -- for divide by 16 signal RxMT_s : boolean; -- Receive register empty signal RxIn_s : std_logic; -- registered serial input signal Parity_Reg : std_logic;
begin -- UartRx_Beh
----------------------------------------------------------------------------- -- Process: Xmit_Lbl -- Purpose: Models the receive portion of a UART. -- Operation is as follows: -- . All operations occur on rising edge of Clk16xT. -- . Clk16xT runs 16x the bit clock rate -- . If ResetF = '0' then -- RxReg_s is reset to "11111111111". -- Count_s is reset to 0. -- . If (RxMT_s and RxIn_s = '0') then -- Start of new byte -- . If Count16_s = 7 and not RxMT_s then -- mid clock -- Sample here where bit most stable -- RxReg_s