Greetings !
I'm looking for a simple RS232 UART16550 receiver for my tiny cyclone board for different baudrates, 8databits, 1stop&startbit and no(!) partity and handshake stuff.
I found several free VHDL implementations in the net but compared to what I need they are to complicated and appear like shooting with missiles on birds ;-)
The entity might have a simple structure like this:
entity receiver is generic( frequency : integer := 10000000; -- e.g. for 10MHz baudrate : integer := 9600 -- e.g. for 9600bps );
port( clk : in std_logic; -- clockspeed is 'frequency' reset : in std_logic; -- resets the receiver receiver : in std_logic; -- input from receive pin from RS232 connector
char_avail : out std_logic; -- indicated that a valid char has beed received char : out std_logic_vector(7 downto 0) -- received char, only available for one clock ); end receiver;
The 'reciever' values are 'active high'...
This structure gives the responsibility for catching received data in time to the user but surely allowes adding a FIFO.
Probably this question has been asked about 47283407239 times in this group so please just send me a usefull link or code snippet...
Konstantin