Typical jitter of high frequency oscillators?

Andreas,

Your question is equivalent to: "If I walk outside, how much noise will I hear?"

Jitter is phase noise. How much phase noise you will "hear" is entirely dependent on "where you live": is there a freeway next to you? Railroad tracks, a forest, a waterfall? Jackhammer? Roadside bomb?

The question, just like jitter itself, is unbounded (there are no theoretical limits to noise, as it is a matter of time until a larger noise comes along).

The "system jitter" will vary of course, depending on primarily: the number of things switching on the same clock edge (both internal, and external), the quality of the bypass solution (was it designed for the clock rate? or is it a generally good solution, or a poor one), and the signal integrity of the IOs (reflections, mismatch, etc.).

I have seen from 50 ps on a pcb with everything done right, to over

Some typical numbers for "I didn't care, and I would be happy with my results" come in from 200 to 500 ps (all peak to peak numbers).

There is a great deal of collateral on the subject on the Xilinx web pages (signal integrity), but this is "still" an unsolved problem, with no tools, and only moderate estimation ability (eg: jitter prediction is built into the ISE software for the DCM and clock resources).

Austin

Hi Andreas, Austin's right! :-)

However, the thing to remember is that it is practicable to be able to predict the noise your oscillator will have before you build it. Noise doesn't just appear for no reason, it comes from many sources. With some work, you can make informed predictions of the performance of a circuit. There's no 'magic' or 'guesswork' to it, just because it's noise. It can be modelled, with good accuracy.

My main method for doing these calculations invariably involves taking my synthesiser designer mate to the pub, and exchanging beer for calculations. He normally yaps on about Leeson's model, how resistors are evil, and diodes are great! YMMV!

But, this is a big, big subject. I've used some stuff in Gardner's PLL book, which I found useful.

HTH., Syms.

Symon,

Glad we agree.

I was trying to answer the more general question "how much jitter will my FPGA add to my pcb?"

For that, there is no 'Leeson's model'. By the way, Dave Leeson is a "neighbor" of mine in the Santa Cruz mountains (the 123 mph winds this month affected us both!). Interesting that his work at California Microwave to explain PLL's to his designers has been carefully converted from his original code to more useful (and modern) tools today. And, all of his napkin 'lectures' converted into white papers, applications notes, and such.

Austin

Using a good but cheap surface-mount crystal oscillator, and with clean single-ended routing to the clock input pin of an fpga, you can get numbers like 2-5 ps RMS jitter, measured cycle-to-cycle, which is what an fpga cares about. Figure that p-p is about 5x RMS. A differential clock, pecl or lvds, is likely to be a bit better, and higher frequency clocks are of course better than slow ones. The clock multipliers unside fpga's, at least in the Spartan 3's, are pretty bad, so use a fast rock and don't multiply if possible.

A lot of XOs lately seem to have fast but weak edges, so they don't drive a matched-impedance pcb trace well. So locate them right at the fpga clock pin, or buffer before driving traces any distance.

John