Typical clock frequencies of FPGA designs

Andreas,

I would love to get my hands on a good (in a statistical sense) set of data on clocks speeds.

Generally speaking, there are some "magic" frequencies that one sees very frequently that are likely to be on some of the 32 global clock resources (in Virtex 4 and 5):

- PCI (33, 66, 100, or 133 MHz

- SONET/SDH (19.44, 77.76, 155.52, 311.04 MHz)

- DDR xRAM (100, 133, 166, 200, 233, 266, 300 MHz)

- PCIe (125 MHz)

- 405PPC (400,200,100 MHz)

... plus all of the various digital video, and other "standards" that are out there for frequencies used by ASIC/ASSP chips that we commonly find ourselves talking to.

I know that the frequencies have jumped dramatically on the IO interfaces, by the number of hits the website gets for signal integrity issues. I strongly suspected this was going to happen six years ago, so I helped put in place the field SI experts for Xilinx, so we could actually help our customers (rather than just pointing them to a page of recommended consultants).

Fighting the trend for increased frequencies, is the desire for lower power. I would say that the average power per "socket" is falling, rather than increasing. If you would have asked me five years ago what the median power was in the Virtex FPGA, I would have said 12 watts. Today I would guess 9 watts. It seems that when a major component of the cost of running something is the air conditioning, customers recognize that they have to design more efficient systems.

Where this "lower power is better" scheme is most evident is in the microprocessor wars between AMD and Intel. Increasing the clock speed is no longer the goal, rather lowering power is the selling factor.

Austin

Me too. :)

My rule of thumb (take with a pinch of salt!):

• Take the manufacturer's headline speed figure for the part * Anything over 66% of this is "fast" * Anything less, but over 33%, is "slow" * Anything less than 33% is a waste of space :-)

As Austin pointed out, there are many reasons why you might design for this or that frequency, and one FPGA design might contain several distinct clock domains, each chosen for a particular purpose. Or there may be several locally-high-speed blocks which communicate over a lower-speed bus.

FPGA vendors' marketing departments doubtless have a lot of data on this, but I suspect they'll be reluctant to let you have it!

Cheers,

-Ben-

I've got a candidate for absurdly low :)

We have a CPLD design for a Clock(time variety) that starts at 32.768KHz, but we divide that a little before the CPLD uses it, so 1024Hz is the CPLD clock. The corner frequency (where the uA/Mhz adds 10% to the Static icc of

" Any frequency that barely moves the meter above Static Icc, qualifies as Absurdly low."

Of course, on some FPGAs, that will be rather high.... ;)

-jg

You didn't mention the CPLD used, but I'm guessing that there are a number of reasons in addition to the maximum achievable clock rate that go into selection of an FPGA for a design. For the lowest cost per I/O parts, for example, I wouldn't be surprised if there were a number of absurdly slow designs running into significant volumes. I'm guessing the CPLD in this case was chosen for minimal power consumption. At 1024 Hz. there are a number of microcontrollers that would do the job of a clock quite nicely.

My FPGA designs often have bits of random house-keeping or control functions that run much slower than the remainder of the design, but often the part is picked for a combination of size (LUTs and flip-flops) and frequency that determine my ability to move data through the part.

As the matrix of options available in the newer FPGA families grows, many parts will be chosen for other features such as built-in SERDES or available block memory rather than the speed of the fabric.

Designs that get close to the manufacturers published clock frequencies become rarer at the larger densities, but quite common in the smallest part of any family. So "absurdly fast" has to be tempered with part size as well as Fmax.

Just my 2 cents, Gabor

Atmel ATF1504BE / ATF1502BE

Yes, and for low IO pin cost.

yes, but at 100 pins, they are more expensive than the cpld, ( as well as being considerably over-resourced !) and this is also partly a teaching example for CPLDs....

Finding a regulator that did not impact the Icc was quite a challenge ...

-jg

I am working on a design where the output rate is 3 Gbps, the fast internal logic runs at 300 MHz, but the bulk is human-oriented GUI, clocked at 1 MHz. What's the average of 3Gbps and 1 MHz?

I suppose big, cutting-edge multi-FPGA designs usually run "as fast as possible", while small, single-FPGA designs might run at all sorts of clock rates. Sometimes faster is not any better, especially in human- oriented control.

BTW, don't assume that our Marketing folks keep exact records of our customers' clock frequencies. But they usually get an earful when the part isn't fast enough...

Peter Alfke

FYI:

I did a low power design, simple enough to fit in a low power CPLD (xc2c64a). In my case the number of I/O was not important.

To implement my system I had to add 2 ext comparators (one to generate clock - 150KHz, one to detect the input) and one LDO because the supply was not regulated.

I did the same design using MCUs (TI and Mirochip): I had to clock them 4x or 6x faster to do same job.

Guess what: the lowest power was required by the design w/ CPLD. Unfortunately it's prohibitive because of the price and [package] size (again, in my case I'd needed one input and one output). I wish they would make low cost CPLD in small packages, about the size of xc2c128, w/ LDO and 1-4 comparators on die.

Also I've found the POR circuitry of this device (xc2c64a) rock solid. I was very impressed with its performance.

-- mmihai

Interesting - so what did you finally go into production with ?

-jg

The latest of our tiny logic analyzers samples at 1GHz, using a Spartan_3. Not too much of the logic runs at 1ns between edges ;-) We managed 500MHz with a Spartan_2.

The web page is

-- Tim

I have a CPLD design with an input clock 153.6kHz (16 x 9600) and most of the design is running at 75Hz.

The CPLD was chosen to be big enough to fit the design and a CPLD was chosen over a microcontroller because microcontrollers need 'software' and in some organisations the amount of crap you have to go through to use any kind of 'software' in a design makes a programmable logic solution attractive.

For V4, 200 MHz isn't high speed, in fact it is only half the clock rate the DSP48's BRAMs and DCMs are spec'd at for the slowest speed grade. At 200 Mhz, you don't really even need to worry much about placement as long as you are reasonably careful with the design. I'd put the dividing line for high speed somewhat over 300 MHz, in other words where you start to have to worry about placement in order to meet timing. My floating point FFT kernel makes timing in a -10 part at 400MHz: it is limited by the clock speed of the BRAM and DSP48s, that probably counts for extremely high, as the clock speed is limited by the minimum clock period of the FPGA blocks rather than by the design. If you stick to just LUTs, you can push it quite a bit higher, but then you give up the big features too. The V4 clocks don't really like to be run slower than about 150 MHz. I'd consider anything less than that to be quite low.

The flip side to this is power consumption. At high utilization and high clock rates, cooling can become a challenge.

FPGAs are much different than CPLDs as far as clocking goes too. FPGAs have an abundance of flip-flops, as well as clock managers that can multiply the input clock. This makes it very attractive to use a multiplied clock in order to reduce the footprint of the logic, which can often get you into a significantly smaller device.