Hi all, I have a microblaze processor that I've built using the EDK and afterwards simulated and it seems to work fine. Now I need to make two instances of this Microblaze system in my design. Can I use the same module and instantiate it twice or I maybe I need to make a copy of the system and name it differently. If I instance the same module twice I figured out that it will be problematic to fill the BRAM with code data. Can anyone help ? Thanks, Mordehay.
Hi Goran, I did not understood your answer.. Do you mean that I need to create a system which contains two microblaze instances and afterwards export it to the ISE ?
What if I want to have these two microblazes in two different systems and afterwards export them to ISE separately (my top.vhd will contain two system (microblaze) instances ? Can I do it ? Can I use two BMM files in that case ?
I haven't tried this myself but you should be able to import two EDK system into a ISE project. You can't have two .bmm but you could merge them into a common .bmm. In a .bmm file there is the hierarchical path to the BRAMs so they should be possible to merge as long the paths are different.
Göran
What if I want to have these two microblazes in two different systems and afterwards export them to ISE separately (my top.vhd will contain two system (microblaze) instances ? Can I do it ? Can I use two BMM files in that case ?
You can instantiate a microblaze system twice in your toplevel. The only problem you have is the .bmm file. This is only describing the memory layout for one system. You can do the following:
- take the generated .bmm file (generated by edk);
- rename it to dual_mb.bmm for instance;
- copy the contents from the file at the end of the file:
- include this .bmm file in your ise project and a dual_mb_bd.bmm file will be created. In your toplevel you should call the instances of your microblaze system respectively transmitter_core and receiver_core (using the example code above);
Now the problem is: how to get the software executable into both memory locations, because importing the .bmm file in the edk won't work (the system is only having one memory layout for one microblaze, while the generated .bmm file has two). You can fix this by manually import the software executable in the generated .bit file. You have to use the tool data2mem. Look at the following line and modify it to your own situation.
data2mem -bm syn\dual_mb_bd.bmm -bt syn\toplevel.bit -bd ..\code\executable.elf tag txc_plb_bram -bd ..\code\executable.elf tag rxc_plb_bram -o b download.bit
I use this solution for a dual powerpc system, but I am sure it will work for the microblaze too.
I had a conference call with xilinx in the past about this issue (using an edk project with one powerpc and instantiate it twice in a vhdl design). They told me that the tools are not made for this functionality. There solution was: make an edk project with both processors. This is not an option if you want to make a common block with one processor which you can instantiate multiple times.
The only problem you could have is debugging your software. With the powerpc system you can only have one jtagppc_cntlr in the fpga. So it must be placed outside the edk project. I gave it a try but was not able to make contact through the edk. The edk simply detected no jtagppc_cntlr in the .mhs file so it assumed there was none in the fpga. I don't know if it would work with the microblaze in combination with the opb_mdm module.
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