Hi,
There's been a few discussions about this the last couple years, but it seems nothing ended with firm conclusions. What I would like to do is to run DDR2 at 25MHz (DDR50). I understand that to do this I have to turn off the DLL (which can't work at below 125MHz) and that this should work but is not supported. My question is, what happens then?
Ie: How do the DQS signals behave during read? Do they turn off, become random, are synchronized with the clock? Is it safe to just read the data a quarter cycle after the clock edge, or is it more complicated than that? I haven't designed an sdram core before, but I'm going to have to do this for this project and have many other, more general questions. If someone knows some good reading material, please let me know.
Aleksandr Dubinsky