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Trying to get plb_temac working

vkogqOf2sHV7VnPd Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable

Hello,

I am using the XilinX Virtex 4 FX 12 Evaluation Kit and want to get ethernet working (it will have to do some IP networking stuff). The board is equipped with an mii-interface so usign hard_temac and plb_temac should be enough (or am I wrong here?). I programmed the FPGA with using these IP cores (and those which the BSB preselected), but the ethernet switch I connected to the board does not recognize anything. Do I make any mistake? Or do I first need to get some software running on the integrated ppc which somehow initializes the ethernet interface?

# #########################################################################= ##### # Created by Base System Builder Wizard for Xilinx EDK 8.1.02 Build EDK_I.2=

0.4 # Mon Sep 4 13:52:39 2006 # Target Board: Avnet Virtex-4 FX12 Evaluation Board Rev 1.0 # Family: virtex4 # Device: XC4VFX12 # Package: FF668 # Speed Grade: -10 # Processor: PPC 405 # Processor clock frequency: 100.000000 MHz # Bus clock frequency: 100.000000 MHz # Debug interface: FPGA JTAG # On Chip Memory : 16 KB # Total Off Chip Memory : 36 MB # - FLASH_2Mx16 =3D 4 MB # - DDR_SDRAM_1 =3D 32 MB # #########################################################################= #####

PARAMETER VERSION =3D 2.1.0

[...]

PORT fpga_0_Ethernet_MAC_PHY_Mii_mdc =3D fpga_0_Ethernet_MAC_PHY_Mii_mdc, = DIR =3D O # # managment data io PORT fpga_0_Ethernet_MAC_PHY_Mii_mdio =3D fpga_0_Ethernet_MAC_PHY_Mii_mdio= , DIR =3D IO # transmit data PORT fpga_0_Ethernet_MAC_PHY_Mii_txd =3D fpga_0_Ethernet_MAC_PHY_Mii_txd, = DIR =3D O, VEC =3D [3:0] # transmit enable PORT fpga_0_Ethernet_MAC_PHY_Mii_txen =3D fpga_0_Ethernet_MAC_PHY_Mii_txen= , DIR =3D O # transmit error PORT fpga_0_Ethernet_MAC_PHY_Mii_txerr =3D fpga_0_Ethernet_MAC_PHY_Mii_txe= rr, DIR =3D O # transmit clock PORT fpga_0_Ethernet_MAC_PHY_Mii_tx_clk =3D fpga_0_Ethernet_MAC_PHY_Mii_tx= _clk, DIR =3D I # carrier sense PORT fpga_0_Ethernet_MAC_PHY_Mii_crs =3D fpga_0_Ethernet_MAC_PHY_Mii_crs, = DIR =3D I # collision detect PORT fpga_0_Ethernet_MAC_PHY_Mii_col =3D fpga_0_Ethernet_MAC_PHY_Mii_col, = DIR =3D I # receive data PORT fpga_0_Ethernet_MAC_PHY_Mii_rxd =3D fpga_0_Ethernet_MAC_PHY_Mii_rxd, = DIR =3D I, VEC =3D [3:0] # receive data valid PORT fpga_0_Ethernet_MAC_PHY_Mii_rxdv =3D fpga_0_Ethernet_MAC_PHY_Mii_rxdv= , DIR =3D I # receive error PORT fpga_0_Ethernet_MAC_PHY_Mii_rxerr =3D fpga_0_Ethernet_MAC_PHY_Mii_rxe= rr, DIR =3D I # receive clock PORT fpga_0_Ethernet_MAC_PHY_Mii_rxclk =3D fpga_0_Ethernet_MAC_PHY_Mii_rxc= lk, DIR =3D I PORT LVDS_N =3D lvds_n, DIR =3D IO, VEC =3D [0:29] PORT LVDS_P =3D lvds_p, DIR =3D IO, VEC =3D [0:29]

[...]

BEGIN plb_temac PARAMETER INSTANCE =3D plb_temac_0 PARAMETER HW_VER =3D 3.00.a PARAMETER C_BASEADDR =3D 0x81200000 PARAMETER C_HIGHADDR =3D 0x8120ffff BUS_INTERFACE MSPLB =3D plb BUS_INTERFACE V4EMACSRC =3D plb_temac_0_V4EMACSRC END

BEGIN hard_temac PARAMETER INSTANCE =3D hard_temac_0 PARAMETER HW_VER =3D 3.00.a PARAMETER C_PHY_TYPE =3D 0 BUS_INTERFACE V4EMACDST0 =3D plb_temac_0_V4EMACSRC PORT MII_TXD_0 =3D fpga_0_Ethernet_MAC_PHY_Mii_txd PORT MII_TX_EN_0 =3D fpga_0_Ethernet_MAC_PHY_Mii_txen PORT MII_TX_ER_0 =3D fpga_0_Ethernet_MAC_PHY_Mii_txerr PORT MII_RXD_0 =3D fpga_0_Ethernet_MAC_PHY_Mii_rxd PORT MII_RX_DV_0 =3D fpga_0_Ethernet_MAC_PHY_Mii_rxdv PORT MII_RX_ER_0 =3D fpga_0_Ethernet_MAC_PHY_Mii_rxerr PORT MII_RX_CLK_0 =3D fpga_0_Ethernet_MAC_PHY_Mii_rxclk PORT MII_TX_CLK_0 =3D fpga_0_Ethernet_MAC_PHY_Mii_tx_clk PORT MDC_1 =3D fpga_0_Ethernet_MAC_PHY_Mii_mdc PORT MDIO_1 =3D fpga_0_Ethernet_MAC_PHY_Mii_mdio END

Reply to
Benedikt Wildenhain
Loading thread data ...

Are you talking about the ML403?

There will be an external PHY on your board. It's likely that you could hook your switch up to this without anything in the FPGA and it would negotiate a link speed and blink the RX lights. If that's not happening, solve that problem before you worry about the FPGA.

--
Ben Jackson AD7GD

http://www.ben.com/
Reply to
Ben Jackson

lEGEL1/lMxI0MVQ2 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable

Hello Ben,

e:

No, I am using the board sold by avnet, see

formatting link
(main advantage: has LVDS pairs which I will need to make accessible using tcp/ip).

This doesn't seem to be the case: When I use an example project using opb_ethernet which directly uses the PHY the switch recognizes that there is a connection. (As I only have a evaluation IP core of opb_ethernet I want to avoid using this one)

Reply to
Benedikt Wildenhain

Did you check if the example project has source code to program the PHY & the Ethernet core? I don't think it will work before doing that.

/Siva

Reply to
Siva Velusamy

Well, that board says it has a National DS83847. Looks like you need to register to get schematics. You should grab the datasheet and see what's required to make it work. Again, if the PHY is set up for autonegotiation it probably doesn't care what's on the MII interface when it comes to negotiating link. It's possible that the configuration and reset lines on the PHY are tied to the FPGA, and it's not the MAC that's the issue, but some glue in the example project which is driving those config lines. It's also possible that the example project configures registers with MDIO before the PHY will work, but I bet it has sufficient hardware configuration as well.

--
Ben Jackson AD7GD

http://www.ben.com/
Reply to
Ben Jackson

are you sure you have all the pin assignments/connections between plb_temac and hard_temac and such set up properly for the board ?

here are the relevant portions of the system.mhs and system.ucf files that i am using (for the same V4FX12 mini module board with the gig phy)

--- system.mhs

PORT hard_temac_0_GMII_RX_CLK_0_pin = hard_temac_0_GMII_RX_CLK_0, DIR = I PORT hard_temac_0_GMII_RX_DV_0_pin = hard_temac_0_GMII_RX_DV_0, DIR = I PORT hard_temac_0_GMII_RX_ER_0_pin = hard_temac_0_GMII_RX_ER_0, DIR = I PORT hard_temac_0_GMII_RXD_0_pin = hard_temac_0_GMII_RXD_0, DIR = I, VEC = [7:0] PORT hard_temac_0_GMII_TX_CLK_0_pin = hard_temac_0_GMII_TX_CLK_0, DIR = O PORT hard_temac_0_GMII_TX_EN_0_pin = hard_temac_0_GMII_TX_EN_0, DIR = O PORT hard_temac_0_GMII_TX_ER_0_pin = hard_temac_0_GMII_TX_ER_0, DIR = O PORT hard_temac_0_GMII_TXD_0_pin = hard_temac_0_GMII_TXD_0, DIR = O, VEC = [7:0] PORT hard_temac_0_GTX_CLK_0_pin = hard_temac_0_GTX_CLK_0, DIR = I PORT hard_temac_0_MDC_0_pin = hard_temac_0_MDC_0, DIR = O PORT hard_temac_0_MDIO_0_pin = hard_temac_0_MDIO_0, DIR = IO PORT plb_temac_0_PhyResetN_pin = plb_temac_0_PhyResetN, DIR = O PORT hard_temac_0_MII_TX_CLK_0_pin = hard_temac_0_MII_TX_CLK_0, DIR = I

....

BEGIN hard_temac PARAMETER INSTANCE = hard_temac_0 PARAMETER HW_VER = 3.00.a BUS_INTERFACE V4EMACDST0 = plb_temac_0_V4EMACSRC PORT GMII_RX_CLK_0 = hard_temac_0_GMII_RX_CLK_0 PORT GMII_RX_DV_0 = hard_temac_0_GMII_RX_DV_0 PORT GMII_RX_ER_0 = hard_temac_0_GMII_RX_ER_0 PORT GMII_RXD_0 = hard_temac_0_GMII_RXD_0 PORT GMII_TX_CLK_0 = hard_temac_0_GMII_TX_CLK_0 PORT GMII_TX_EN_0 = hard_temac_0_GMII_TX_EN_0 PORT GMII_TX_ER_0 = hard_temac_0_GMII_TX_ER_0 PORT GMII_TXD_0 = hard_temac_0_GMII_TXD_0 PORT GTX_CLK_0 = hard_temac_0_GTX_CLK_0 PORT MDC_0 = hard_temac_0_MDC_0 PORT MDIO_0 = hard_temac_0_MDIO_0 PORT REFCLK = sys_clk_s PORT RESET = plb_temac_0_Emac_Reset PORT MII_TX_CLK_0 = hard_temac_0_MII_TX_CLK_0 END

BEGIN plb_temac PARAMETER INSTANCE = plb_temac_0 PARAMETER HW_VER = 3.00.a PARAMETER C_BASEADDR = 0x80400000 PARAMETER C_HIGHADDR = 0x8040ffff PARAMETER C_PLB_CLK_PERIOD_PS = 10000 PARAMETER C_DMA_TYPE = 1 PARAMETER C_RX_DRE_TYPE = 0 PARAMETER C_TX_DRE_TYPE = 0 PARAMETER C_RXFIFO_DEPTH = 65536 PARAMETER C_TXFIFO_DEPTH = 65536 BUS_INTERFACE MSPLB = plb BUS_INTERFACE V4EMACSRC = plb_temac_0_V4EMACSRC PORT IP2INTC_Irpt = plb_temac_0_IP2INTC_Irpt PORT PhyResetN = plb_temac_0_PhyResetN PORT Emac_Reset = plb_temac_0_Emac_Reset END

--- system.ucf

Net hard_temac_0_GMII_RX_CLK_0_pin LOC=W11 | IOSTANDARD = LVCMOS33; Net hard_temac_0_GMII_RX_DV_0_pin LOC=J6 | IOSTANDARD = LVCMOS33; Net hard_temac_0_GMII_RX_ER_0_pin LOC=H1 | IOSTANDARD = LVCMOS33; Net hard_temac_0_GMII_RXD_0_pin LOC=J5 | IOSTANDARD = LVCMOS33; Net hard_temac_0_GMII_RXD_0_pin LOC=K3 | IOSTANDARD = LVCMOS33; Net hard_temac_0_GMII_RXD_0_pin LOC=J4 | IOSTANDARD = LVCMOS33; Net hard_temac_0_GMII_RXD_0_pin LOC=K4 | IOSTANDARD = LVCMOS33; Net hard_temac_0_GMII_RXD_0_pin LOC=M6 | IOSTANDARD = LVCMOS33; Net hard_temac_0_GMII_RXD_0_pin LOC=L2 | IOSTANDARD = LVCMOS33; Net hard_temac_0_GMII_RXD_0_pin LOC=K1 | IOSTANDARD = LVCMOS33; Net hard_temac_0_GMII_RXD_0_pin LOC=K2 | IOSTANDARD = LVCMOS33;

Net hard_temac_0_GMII_TX_CLK_0_pin LOC=M2 | IOSTANDARD = LVCMOS33; Net hard_temac_0_GMII_TX_EN_0_pin LOC=N2 | IOSTANDARD = LVCMOS33; Net hard_temac_0_GMII_TX_ER_0_pin LOC=P1 | IOSTANDARD = LVCMOS33; Net hard_temac_0_GMII_TXD_0_pin LOC=M4 | IOSTANDARD = LVCMOS33; Net hard_temac_0_GMII_TXD_0_pin LOC=N4 | IOSTANDARD = LVCMOS33; Net hard_temac_0_GMII_TXD_0_pin LOC=L1 | IOSTANDARD = LVCMOS33; Net hard_temac_0_GMII_TXD_0_pin LOC=M1 | IOSTANDARD = LVCMOS33; Net hard_temac_0_GMII_TXD_0_pin LOC=P2 | IOSTANDARD = LVCMOS33; Net hard_temac_0_GMII_TXD_0_pin LOC=N5 | IOSTANDARD = LVCMOS33; Net hard_temac_0_GMII_TXD_0_pin LOC=P4 | IOSTANDARD = LVCMOS33; Net hard_temac_0_GMII_TXD_0_pin LOC=P5 | IOSTANDARD = LVCMOS33;

Net hard_temac_0_MII_TX_CLK_0_pin LOC=Y5 | IOSTANDARD = LVCMOS33; Net hard_temac_0_GTX_CLK_0_pin LOC=W9 | IOSTANDARD = LVCMOS33; Net hard_temac_0_MDC_0_pin LOC=J3 | IOSTANDARD = LVCMOS33; Net hard_temac_0_MDIO_0_pin LOC=N3 | IOSTANDARD = LVCMOS33; Net plb_temac_0_PhyResetN_pin LOC=M3 | IOSTANDARD = LVCMOS33;

--
works for me !

note the connection from the plb_temac to the reset pin on the PHY, if
this is missing you probably won't get a link...

-rimas

Benedikt Wildenhain wrote:
> Hello,
>
> I am using the XilinX Virtex 4 FX 12 Evaluation Kit and want to get
> ethernet working (it will have to do some IP networking stuff). The board
> is equipped with an mii-interface so usign hard_temac and plb_temac
> should be enough (or am I wrong here?). I programmed the FPGA with using
> these IP cores (and those which the BSB preselected), but the ethernet
> switch I connected to the board does not recognize anything. Do I make any
> mistake? Or do I first need to get some software running on the
> integrated ppc which somehow initializes the ethernet interface?
>
Reply to
funkrhythm

Absolutely not ;-). Thanks for your information. (And for the other mails, too). I'll be away some days, but I hope it will start working next week.

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May the tux be with you.  :wq 73
Reply to
Benedikt Wildenhain

Fba/0zbH8Xs+Fj9o Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable

Hello,

=3D > O xst complained when trying to set the direction to output for mii, so I set it to input.

Now I want to try sending some IP packets accross the wire, but both xilnet and lwip insist on using either opb_ethernet or -lite. Are there any adjusted versions for one of these?

Reply to
Benedikt Wildenhain

hmmm... that particular signal (tx_en) is definitely an output, as are about half of the MII signals

don't know about that, i am running linux on the V4FX12 and the EDK generates an ethernet driver (xilinx_gige) that works with the PLB_TEMAC

-rimas

Reply to
funkrhythm

How did you compile a matching kernel? I tried to compile a 2.4 kernel (I tried several branches, but finally got farest with the branch from bee2.eecs.berkeley.edu as it already has integrated the xilinx_gige driver) with the BSP for Montavista Linux 3.1. As (menu|x)config doesn't offer my board I set CONFIG_MEMEC_2VPX=y, tried to compile it with support for uartlite (for the serial console) and xilinx_gige, but linking the kernel fails with

/space/benedikt/crosstool/gcc-3.4.1-glibc-2.3.3/powerpc-405-linux-gnu/bin/powerpc-405-linux-gnu-ld

-T arch/ppc/vmlinux.lds -Ttext 0xc0000000 -Bstatic arch/ppc/kernel/head_4xx.o init/main.o init/version.o init/do_mounts.o \ --start-group \ arch/ppc/kernel/kernel.o arch/ppc/platforms/platform.o arch/ppc/mm/mm.o arch/ppc/lib/lib.o kernel/kernel.o mm/mm.o fs/fs.o ipc/ipc.o arch/ppc/math-emu/math-emu.o arch/ppc/xmon/x.o \ drivers/char/char.o drivers/block/block.o drivers/misc/misc.o drivers/net/net.o drivers/macintosh/macintosh.o drivers/media/media.o \ net/network.o \ /space/benedikt/tfc/bee2.eecs.berkeley.edu/linuxppc-2.4/lib/lib.a \ --end-group \ -o vmlinux arch/ppc/platforms/platform.o(.text.init+0x3e): In function `board_io_mapping': : undefined reference to `rs_table' arch/ppc/platforms/platform.o(.text.init+0x46): In function `board_io_mapping': : undefined reference to `rs_table' arch/ppc/xmon/x.o(.text+0x64): In function `xmon_map_scc': : undefined reference to `__sysrq_put_key_op' make: *** [vmlinux] Error 1

Later I tried to create an auto-config.in with the BSP for uclinux, but this also failed:

Running generate for OS'es, Drivers and Libraries ... #-------------------------------------- # uClinux BSP generate... #-------------------------------------- ERROR:MDT - ERROR FROM TCL:- uclinux () - expected integer but got "" while executing "format "0x%08x" $mem_start" (procedure "do_memory_setup" line 64) invoked from within "do_memory_setup $config_file $os_handle "FLASH_MEMORY" CONFIG_XILINX_FLASH" (procedure "::sw_uclinux_v1_00_d::generate" line 23) invoked from within "::sw_uclinux_v1_00_d::generate 148725840" TARGET_PERIPH: hard_temac_0 ARG: C_PHY_TYPE VALUE: 0 ERROR:MDT - Error while running "generate" for processor ppc405_0... make: *** [ppc405_0/lib/libxil.a] Error 2

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Fingerprint = 9C03 86B5 CA59 F7A3 D976  AD2C 02D6 ED21 E32C 4F4B
Mit freundlichen Gruessen | Kun afablaj salutoj (www.esperanto.org)
May the tux be with you.  :wq 73
Reply to
Benedikt Wildenhain

i used the branch of the ppc kernel mentioned here

formatting link

and copied over the files from the BSP

then what i did was to edit the Makefile in the drivers/net directory and change the references from xilinx_enet to xilinx_gige, and select the regular xilinx driver in the menuconfig

-rimas

p.s. if the PVR (processor version register) in your mini-module is

0x20011430 make sure you apply patches to turn off caching or you will have problems. more info here:

http://www.xil> Hello,

Reply to
funkrhythm

Is anyone using linux 2.4 with the plb_temac? And what about EDK 7.1? I am having difficulty finding a linux driver for the plb_temac with

2.4.

Rimas, when you say that you used the xilinx_gige driver, will that work for the plb_temac? What about the xparameters*.h defines where they use _XTEMAC_ rather than _XGEMAC_?

-cy

funkrhythm wrote:

formatting link

Reply to
corley

i am using EDK 8.1... it sounds like 7.1 didn't have the driver for the plb_temac (which is in the BSP generated by 8.1 in drivers/net/xilinx_gige)

-rimas

corley wrote:

formatting link

Reply to
funkrhythm

i am using EDK 8.1... it sounds like 7.1 didn't have the driver for the plb_temac (which is in the BSP generated by 8.1 in drivers/net/xilinx_gige)

-rimas

corley wrote:

formatting link

Reply to
funkrhythm

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