I am unable to infer a True Dual Port RAM in ispLEVER using VHDL. I'm targetting the Lattice ECP2M using Synplify. Even the provided example located in isptools7_0\examples\fpga\latticexp2\memory\inferencing\true_dual_port\vhdl\true_dual_port.vhd does not synthesize successfully. Has anyone else had any better luck at this?
Thanks, Colin
isptools7_0\examples\fpga\latticexp2\memory\inferencing\true_dual_port\vhdl\true_dual_port.vhd
It works fine with Precision. I too had the same problem with Synplify ver
8.1 IIRC. It appears that template is all wrong for Synplify. Try another one from Sunplify user guide...Happy inferencing :)
Maki.
Switching to Precision certainly did the trick. I've also alerted Lattice about the issue with Synplify and they've been very responsive. So hopefully it will soon be resolved. Although, I think I might just stick with Precision.
isptools7_0\examples\fpga\latticexp2\memory\inferencing\true_dual_port\vhdl\true_dual_port.vhd
ly
vhdl=AD\true_dual_port.vhd
ter
rHow does everyont simulate True Dual Ports with VHDL? I've got synplicity working fine with simple behavioral code but it has two seperate processes accessing the same memory array (one for port A, another for port B). My simulator can't handle this situation.
Do you need to work around this problem by writing a seperate, non- synthesizable version of the dual port just for simulation?
Just curious...
Pete
IIRC I used template for dpram with shared variables for XST and for simulation. But this template for Precision is strange...
Best regards, Maki.
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