Hi:
I'm trying to use a memory in a Verilog testbench to generate arbitrary waveforms to stimulate my Verilog module.
I'm using ModelSim XE II/Starter 5.7c with Xilinx Webpack 5.2i.
Modelsim complains with this message:
# Model Technology ModelSim XE II vlog 5.7c Compiler 2003.03 Mar 15 2003 # -- Compiling module testbench # ** Error: E:/xilinx/CPLD-Magic-Box/cummins-camprox/testbench.tf(4): near "$readmemh": syntax error vlog -reportprogress 300 -work work {E:/xilinx/CPLD-Magic-Box/cummins-camprox/testbench.tf}
The offending line of testbench code looks like this:
------------------------------------------- module testbench();
reg [3:0] wave [0:191]; // create 192 x 4-bit waveform data table
$readmemh( "testhex.txt", wave ); // Load RAM from file
endmodule
-------------------------------------------
The text file looks like:
-------------------------------------------
4'h1 //count1(referringtothe74LS193datahere) 4'h1 4'h1 4'h14'h0
4'h0 4'h0 4'h04'h1 //count2
4'h1 // etc.--------------------------------------------
Any clues?
Thanks.