Tri-Stae Bus

Hello All,

I am developing a partial reconfigurable system that allows modules to be dynamically placed and removed at run-time on Virtex XCV1000 FPGA. As part of my effort I have to develop a shared memory bus through which all these modules can communicate. Inorder to accommodate the partial reconfiguration, the only option left is to implement the bus using tri-state logic (bus macros). There is an central arbiter responsible to generate the enable signal for each of the modules. This enable signal controls the tri-state inputs of the Shared bus signals (Data,Address). I have an address bus of width 19 bits and data bus of width 40 bits. So the enable signal output is to be connected to nearly

50 tri-state input pins.

Is there a limit on the maximum number of signals that an output can drive? Incase if the fanout requirements are not met then the only alternative I could think of was to generate multiple enable signals for each module and use each of these to drive the shared signals. I was wondering if there would be any issues in this approach or if there are any better approaches

Thanks

Reply to
FPGA05
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The limit will depend on the speed that of the busses, the number of loads and the location of the loads. I've found that 50 loads is no problem on a 33MHz bus in the spartan2E.

Incase if the fanout requirements are not met then the only

Reply to
aa55

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