If anyone is still interested in Transputers, I am now releasing the
1st half of a new FPGA Transputer through email, mostly docs but also an Instruction Set simulator, the C cycle model and Verilog sources for later, all works in progressbetter than spam I presume
see comp.sys.transputer
regards all
johnjakson at usa dot com
for
Much better, was April 1st a pre-meditated release date ? :)
Cheers, Rupert
Hi Rupert
No actually I was shooting for last Thanksgiving, then Xmas, then return from Taiwan a month ago, its just a question of whether rotating through the ISA simulator, the C cycle model, the verilog code or the compiler and not letting anyone in or polish up some existing docs and open the door a crack. for some comments or exposure and maybe some help.
Actually I keep wondering why JS doesn't do a ISA simulator too, then I admitted I hadn't either, buts its needed to verify the much more complex cycle model that was my baseline so thought it would be a good idea to describe the IS as simply as a ISA simulator does and release that openly. Not actually giving the whole farm away, yet.
Anyway what with Cell getting some air time I wouldn't want people to think that that was an acceptable Transputer replacement unless somebody tells me they are seriously porting Occam to it, nothing Transputer like has really showed up yet.
I'll stick you on the list anyway.
regards
johnjakson at usa dot com
PS anyway thanks for your previous efforts and being the ideas soundboard, much of that stuff is now starting to work its way through the models.
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