Has anyone ever been able to get Modelsim to model transport delays in Verilog? Verilog simulators, by default, use inertial delays, so if you have an assignment such as this:
assign #4 sig_out = sig_in;
then any pulse on sig_in that is less than 4ns will get swallowed. Modeling transport delays prevents this from happening. Modelsim claims to model transport delays using the +transport_int_delay option for vsim, but this just doesn't seems to work.
-Kevin