All,
Thanks to those who made a nice comment about my post.
(You will note I did not say anything about X vs. A.)
I feel that the question is vendor agnostic: right now the question is about what is different?, not "who should I be using?" It doesn't help at all to recite a litany of features of a tool that they have never even seen, for a design flow that they have never used!
So, to answer more questions ---
"I am more concerned about the rest of things like the synthesis,P&R.
As you pointed out , application of constraints for synthesis, selecting the speed grade etc.."
Synthesis is done by the synthesis tools. As has been often posted here, the quality of the synthesis depends on many things, and you will have to match your style, to your favorite tool (or if you do not have a favorite, pick a few, and try them). I feel that since coding style is often unique to each coder/application, the results are also highly variable.
Place and route is done by the FPGA vendor's tool, after synthesis, and the results are such that you don't get to play here much at all.
For everyone, there are absolute constraints, and relative constrains, which will get you in more trouble than they are worth (generally). Often a designer will have no placement constrains, nor pin constraints, and see what happens. If they don't like the result, they may start first by locating the IO bus pins in a preferred logical way, and move on from there (you quickly realize IO comes in 'banks', and that keeping IO in banks that are adjacent for the same function is a smart move).
WARNING: (Potential) Marketing Message*: If you are doing very high end work, then the ONLY tool out there is PlanAhead, which Xilinx owns now, for FPGA. It allows general area constraints, and nailing down inside IO locations of your function blocks and your IO pin locations outside. :End of WARNING!
*Message does contain truthful statements about capabilities, however.
Constraints is all something that will be specific to your synthesis tool, and how well you can speak its constraint language. Unfortunately, there is little standardization here (everyone likes to be just a tiny bit different).
Speed grade is easy: choose the slowest, work as hard as you can, and only go to the next faster grade if there is no way to make your design meet timing. Speed grades cost more money, so this is a naturally regulating design issue.
And, we all have to begin somewhere. Xilinx does offer classes, both introductory and advanced, across a wide range of topics.
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I am told by one of my compatriots that his classes that he teaches at a local university are often attended by ex-ASIC designers, being interested in getting educated about use of FPGAs.
I am sure that you have universities and colleges in your area that offer such classes. The key is that you need to be sure that they are using a FPGA for their lab part of the course, and the course is current to the technology.
FPGA vendors (usually) have free software packages that support the smaller devices, and perhaps have a few less features, but are excellent learning platforms.
WARNING! (Potential) Marketing Message: For example, Spartan 3 and 3E have sold tens of thousands of student boards to university programs around the world, making them one of the most successful teaching platforms, ever. The cost is on par with most college textbooks.
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:End of WARNING!
Austin