hey guys i hope u can help me out... i want to design a simple traffic light controller according to the 4 states shown in the code below. my only problem is that my signal state_reg is not changing form one state to another. this is because the counter i included in the the code as a process is not working. green to yellow time wait is 30 sec and yellow to red is 5 sec. my clock period will be 5 sec. so can anyone help me out
---------------------------------------------------------------------------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use IEEE.std_logic_unsigned.all;
entity TLC is port( clk,reset, sa, sb:in std_logic; Ga, Ya, Ra, Gb, Yb, Rb:out std_logic ); end TLC;
architecture Behavioral of TLC is
type state_type is (a, b, c, d); signal state_reg, state_next: state_type; signal Pre_Q, Q: std_logic_vector(3 downto 0); signal count, clear: std_logic;
begin
-- behavior describe the counter process(clk, count, clear) begin if (clear = '0') then Pre_Q