Traffic Light with counter

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First, I would stongly suggest you use numeric_std instead of std_logic_arith, especially when you're learning, since it's the accepted standard. Next, remember that at the start of simulation, all of your std_logic signal and output values are 'U', or unspecified. Any operation you perform where one of the operands is 'U' will most likely return 'U', so at some point you've got to give them a concrete value if you want anything to happen.

Also, in a case statement, if you want to cover multiple cases, use "when a | b =>", not "when a => when b =>". That's the way it's done in C, not VHDL.

These aren't all the problems, but hopefully this will set you on the right track.

Hey tang, You should try comp.lang.vhdl . There are a bunch of blokes over there who _really_ know how sensitivity lists work. Ask for Mike xor Jonathan orif Jim. They're among the best at homework. Tell them I sent you. HTH., Syms. p.s. These days, 'traffic light vhdl' is at 159000 Google hits. Adding lumberjack to the search gets you down to a more sensible 39. Only two worse than adding omg ponies. (Thanks to Ben J. for that insight!) Be sure to turn off 'safe search'.

Symon, you are A Very Bad Person. I can think of nations less tolerant and inclusive than ours where this sort of incitement to technical hatred could get you a stiff sentence (something along the lines of "This sentence is inflexible"?).

There are a large number of ways you could do this. Personally I'm not a get fan of next state, current state, style you use but it does have it's followers.

Staying with what you have I would check the asychronous (combinatorial) processes have complete sensativity lists. Your clocked processes I would make sure all statements lie with the clock and reset statements.

Personally I would have a counter that reloaded with values linked to the transitions of the state machine and taking a count value relevant to the state being entered. The counter then counts down to zero and then the next state transition. If you make your counter integer type you don't need extra numerical type libraries.

John Adair Enterpo> hey guys i hope u can help me out... i want to design a simple traffic

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Thanx for the solution. I was also thinking about making counter integer. Can you please elaborate on that? will it be like adding for loop till count reach to desired value and then perform the transition? thanx again

guys i hope u can help me out... i want to design a simple traffic

thanx for the reply...

farm_traffic takes it down to one.

-- Mike Treseler

Sorry Mike, it's two now - and this post will make it three :-)

-- Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK snipped-for-privacy@MYCOMPANY.com

The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.

My gosh, you're right....it just keeps a growin, will it never end????

Can get it back down to 1 though by filtering out anything with the following words

mike treseler wrote jonathan bromley

KJ

"KJ" writted in message news:Fam4j.2769$ snipped-for-privacy@nlpi068.nbdc.sbc.com...

Not now. Myss.

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How many mega herzts will your red light controller run at ?

Start by defining a state machine that has all the states you need and outline the transitions you need qualified with counter. An example (NOT SYNTAX CHECKED) of 4 states below.

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;

ENTITY TRAFFIC IS PORT( CLOCK : IN STD_LOGIC; RESET : IN STD_LOGIC;

OP1 : OUT STD_LOGIC; OP2 : OUT STD_LOGIC); END TRAFFIC;

ARCHITECTURE A0 OF TRAFFIC IS

SIGNAL COUNTER : INTEGER RANGE 0 TO 10000000;

TYPE SM_TRAFFIC_TYPE IS( SM_TRAFFIC_IDLE , SM_TRAFFIC_OP1_ON , SM_TRAFFIC_OP2_ON , SM_TRAFFIC_OP1_OP2_ON );

SIGNAL SM_TRAFFIC : SM_TRAFFIC_TYPE;

BEGIN

TR1 : PROCESS(RESET,CLOCK) BEGIN IF (RESET = '1') THEN SM_TRAFFIC > a get fan of next state, current state, style you use but it does have

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