Hi all,=20 I'd like to highlight a problem encountered while using the Xilinx = foundation series 4.1i. I am unable to connect all the input ports to = the respective output ports due the following comments shown:=20 Too many signals: Checking for sourceless, loadless nets and multiple = drivers aborted.=20 I suspect that there is a limit to the number of bus terminal labels = that we can give on a schematic.=20 The bus terminal labels are given to the inputs and outputs ports so = that they need not to be physically connected with wires. These termianl = labels are essential as it is impossible to physically connect the ports = together with wires under the constraint of the space given in the = schematic.
Any idea how to solve the problem ???
Thanks.
Buzz