Hi, I'm implementing a ddr-fifo buffer and when viewing the synthesis report on the ddr-fifo buffer by itself the timing summary is:
--------------- Speed Grade: -10
Minimum period: 6.976ns (Maximum Frequency: 143.343MHz) Minimum input arrival time before clock: 6.546ns Maximum output required time after clock: 4.543ns Maximum combinational path delay: No path found
When adding a 5 bit counter and 4 if statements that changes the values of wr_en and rd_en on the ddr-fifo the timing summary is:
--------------- Speed Grade: -10
Minimum period: 13.964ns (Maximum Frequency: 71.611MHz) Minimum input arrival time before clock: 6.546ns Maximum output required time after clock: 4.543ns Maximum combinational path delay: No path found
The maximum frequency is about half of the original!
Is this due to the fact that it take some time before the wr_en and rd_en pins in the fifo is effective? So there might be some error on the first and last bits of data.
For me it's okay that the head and tail is corrupt, it is the bits in beteween that are important to my project.
Could I then forget about this timing summary and run the system at the higher clock frequency?
Cheers