Timing summary

Hi, I'm implementing a ddr-fifo buffer and when viewing the synthesis report on the ddr-fifo buffer by itself the timing summary is:

--------------- Speed Grade: -10

Minimum period: 6.976ns (Maximum Frequency: 143.343MHz) Minimum input arrival time before clock: 6.546ns Maximum output required time after clock: 4.543ns Maximum combinational path delay: No path found

When adding a 5 bit counter and 4 if statements that changes the values of wr_en and rd_en on the ddr-fifo the timing summary is:

--------------- Speed Grade: -10

Minimum period: 13.964ns (Maximum Frequency: 71.611MHz) Minimum input arrival time before clock: 6.546ns Maximum output required time after clock: 4.543ns Maximum combinational path delay: No path found

The maximum frequency is about half of the original!

Is this due to the fact that it take some time before the wr_en and rd_en pins in the fifo is effective? So there might be some error on the first and last bits of data.

For me it's okay that the head and tail is corrupt, it is the bits in beteween that are important to my project.

Could I then forget about this timing summary and run the system at the higher clock frequency?

Cheers

Reply to
Kalle
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I plan to run it at 100 MHz... using a DCM to generate 250 MHz and IDDR memories that can receive data at 500 MHz..

Reply to
Kalle

Kalle wrote: [reformatted to make original readable]:

If you open up timing analyzer, it should tell you what is causing the timing violation. Doing anything except that is just making guesses. Guesses like:

Do you have a PERIOD constraint set in your .ucf file?

It's kinda strange that your input and output delays are as high as they are. Are the IOB FF's being used?

Without seeing the VHDL or timing analyzer report for this path, it is impossible to say what is wrong. It seems safe to say that you added a level of logic, but doing so should probably not have slowed things down as much as it looks like it did - so something else is probably up.

Are you sure about that?

You generally don't want to ignore the timing summary unless you have a very good reason to do so. Although the numbers it provides are generally conservative, you can't rely on anything except what the timing reports give you.

I think you mean that your input clock is 100 MHz, but you want to run your logic at 250 MHz, with the data running effectively at 500 MHz (250 MHz DDR) - correct? That should all be doable, although 250 MHz DDR requires attention to board layout, clock delays, etc.

Good luck,

Marc

Reply to
Marc Randolph

Use Timing Analyzer, it's good to see the critical path. Make sure also that I/O flipflops are used. but there is nothing wrong with this report, unless you made a copy-paste mistake that dramatically changes logic. if you add 5-bit counter and 4 "if" statements, it could be mapped into more than one slice. Plus if the design is consuming too much (80+ percent or so), routing can be using LUTs.

Hope this helps.

Vladislav

Reply to
Vladislav Muravin

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