Timing simulation

In that case, *this* idea will be great:

I would synchronize the design and run static timing analysis to verify Fmax. I would use simulation only to verify function.

-- Mike Treseler

Mike,

Does this mean that I do not perform timing simulation and only perform functional simulation?

Functional simulation will verify the function and I have successfully done that but when I perform the timing simulation then I am having some problems to check out the functionality.

I do have period consntarints on the clocks and I am meeting this constraint.

Eddie

functional simulation?

For a synchronous design, yes.

With no constraints, most tools report the Fmax as is.

-- Mike Treseler

Mike,

I am using V5LXT and its GTP. At this point I am doing the simulation of the logic in the FPGA fabric that is feedting the data to the GTP transmitters. When I do the functional simulation, everything looks good but when I do the timing simulation I am not seeing simple logic in the FPGA fabric work. This is why I am intertested in looking at the Fabric logic state machine using timing simulation.

The only thing that I can think of is to bring the fabric state machine outside on the FPGA pins. This will force the software to preserve the names.

Eddie.

Eddie,

What Mike is saying to you is that if your design is synchronous performing timing simulation on it is a waste of your time.

/Mikhail

Yes. I have done the functional simulation and that seems to work fine. So I was curious about the timing simulation. I will work on doing the static timing analysis and see what Fmax I get. I have multiple clock domains so I am hoping that it will provide multiple Fmax values.

Thanks.

Eddie

Thanks.

CP

Fmax values.

I would make separate entities for each clock domain and run STA separately for each.

Then work out synchronization between the domains.

-- Mike Treseler