Hi all... After i synthesize my code i get the following timing reports in my synthesis report file.
Minimum period: 11.536ns (Maximum Frequency: 86.685MHz) Minimum input arrival time before clock: 22.952ns Maximum output required time before clock: 7.829ns Maximum combinational path delay: No path found
Now it says maximum frequency as 86.685 MHz. But at the same time the minimum i/p arrival time before clock is
22.952 ns. So in this case what will be my maximum clock frequency of operation ? Also can anyone explain the significance of all the tree timing parameters listed above. That will b of some help to me. Thanx a lot. puneet
First of all realize that the synthesis timing report is just an estimate of final timing and may be significantly different than the post place-and-route results.
Minimum period only looks at paths that start at a flip-flop and end at another flip-flop. Thus it won't include for example timing from an external input to the first clocked component. In this case it says that from one rising clock edge to the following rising edge some signal will leave a flip-flop in your design and just meet the destination flip-flop's setup timing requirement in
11.536ns. Actually I can only guess at this. If your design uses both edges of the clock, the minimum period may be computed from a path that goes from one clock edge to the other, based on a 50% duty cycle clock. This sort of path will be much easier to determine in the back-end timing reports.
Minimum input arrival time before clock is your input setup time. Since it is longer than the reported period it may indicate that the design won't run at 86.685 MHz, but this depends on how you sample your inputs (specifically those causing the longest input path delays). If you don't get a new sample on every clock or if the maximum time path is your reset signal, your design might still run at 86.685 MHz.
Maximum output required time before clock would be your output clock to Q timing. This indicates that an external device can assume outputs valid by waiting 7.829ns after the clock edge before sampling the signal.
Maximum combinational path delay is only for paths that start at an input to the design and go to an output of the design without being clocked along the way.
Input and output timings are especially dubious in the synthesis-level timing report. It's hard to imagine that the synthesizer can report these numbers before knowing whether the mapper will force flip-flops into the IOB's (other than instantiated components). These timing reports are mostly to give you an idea whether you're in the right ballpark to meet your timing requirements, so for example I wouldn't try to run this design at 120 MHz.
Hi Gabor, That was really wonderful piece of information and also explained quite nicely. Actually after map i got a speed of 123 MHz and after place n route it came to 79.001 MHz. Once again thank you very much.
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