Dear All,
I would like to ask you some timing questions.
First scenatio and first question:
I have two signals, for example, /CS and /RD. Looking at the device datasheet it says that:
-tCLRL CS LOW to RD LOW 0 ns
-tRHCH RD HIGH to CS HIGH Intel mode 0ns
Then looking at the datasheet I must assert /CS before /RD and de-assert /CS after /RD. I would like to know if it is possible to Assert /CS and /RD in the same clock cycle or should I first assert /CS in a clock cycle and in the next clock cycle assert /RD. I mean, in my state machine would be ok to assert /CS and /RD in the same cycle due to "0ns" of the tCLRL and tRHCH or should I use two clock cycles?.
And second scenario and question:
RULE 2.58: During read cycles, the responding SLAVE MUST release all of D00-D31 before releasing DTACK* or BERR* to high.
In a Read Data cycle in an VME Slave when the slave places the data and asserts the signal /DTACK, waits until detects that /DS is high again (Master). Then must release the data bus and rise (de-assert) /DTACK at least "0ns" after releasing the data bus.
Could I release the Data bus and de-assert /DTACK in the same clock cycle or should I release the data bus in a clock cycle and de-assert /DTACK in the next clock cycle?.
Thanks a lot and best regards,
Javi