Timing not met but working on board

It may be because u are not yet applied any test vectors which will violate the 50MHz+ timings..... That may be the one reason why it is working on the board....

Un bel giorno J.Ram digitò:

As far as I know, the timing extimations in ISE are made assuming always the worst case scenario (worst temperatures, worst limit of each specified parameter, etc). They represent a "lower performance limit", but for the actual speed limit I've noticed a lot of difference between the extimation and the reality, especially in blocks with few gates. For example in a SpartanII design I have a 8-bit gray counter incremented by an external clock that in reality exceeds 250 MHz of performance, while the timing extimations suggest a maximum frequency that barely exceeds 100 MHz.

What is wrong is your expectation that based on a sample of one board that works at 90 MHz, that all boards over all rated temperature conditions over all possible input conditions will also work at that speed.

It's not at all unusual to expect that a single board in a lab environment might happen to work at ~50% over the speed computed by the timing analyzer. Try building thousands of such boards and put them in the extreme rated temperature conditions and give them the most stressful input pattern and see how many of those boards still work. What you'll likely find is a lot of fallout...but again you might have a few survivors.

KJ

Can we say that is ~50%....

It's not the *entire* chip that's limited to 56 MHz. Use the Xilinx Timing Analyzer to determine which paths are failing timing. This will both inform you as to where you might see the failure show up (e.g., if it's an accumulator to a register read by software, you'll only know it's a problem if you know what the count should be when/if you read it). It will also give you an idea of where to recode your RTL to achieve 100% timing.

True. Another aspect is that static timing analysis is pessimistic. The slowest path reported might be a path that is never switching in the design scenario at hand or even can't switch under any circumstances (false path).

Kolja Sulimma

KJ nailed it.

Andy

What is wrong is that you are running the part out of spec. It might work fine on some particular chips at room temperature, and fail on other chips or at elevated temperatures.

If you modify the design to meet timing, then it will work on all chips over the rated temperature range.