Timing Error in edk 7.1i

hi all, we are getting the following timing error...........the timing analyser does not show any error ......

Asterisk (*) preceding a constraint indicates it was not met. This may be due to a setup or hold violation.

--------------------------------------------------------------------------------

TSCLK2CLK90_DDR_SDRAM_64Mx32 = MAXDELAY F | 2.500ns | 2.543ns |

1 ROM TIMEGRP "OPB_Clk_DDR_SDRAM_64 | | |

Mx32" TO TIMEGRP "Device_Clk90_in | | |

_DDR_SDRAM_64Mx32" 2.5 ns | | |

-------------------------------------------------------------------------------- TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_ | N/A | N/A | N/A pin" 10 ns HIGH 50% | | |

-------------------------------------------------------------------------------- TS_dcm_0_dcm_0_CLK0_BUF = PERIOD TIMEGRP | 10.000ns | 9.966ns |

10 "dcm_0_dcm_0_CLK0_BUF" TS_sys_clk_pin | | |

HIGH 50% | | |

-------------------------------------------------------------------------------- TS_dcm_0_dcm_0_CLK90_BUF = PERIOD TIMEGRP | 10.000ns | 6.628ns | 1

"dcm_0_dcm_0_CLK90_BUF" TS_sys_c | | |

lk_pin PHASE 2.5 ns HIGH 50% | | |

--------------------------------------------------------------------------------

1 constraint not met. INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value. Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 12 mins 21 secs Total CPU time to PAR completion: 11 mins 45 secs

Peak Memory Usage: 216 MB

Placement: Completed - No errors found. Routing: Completed - No errors found. Timing: Completed - 4 errors found.

thanx........