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Timing constraints in ucf

I'm a bit new to FPGA configuration and I couldn't find any messages that addressed my particular problem (although I'm sure this is a common issue). I am using the Xilinx ISE Webpack to configure a Spartan 3 FPGA. I am multiplexing a 16-bit data bus and routing it to differend devices. I want to control the signal-to-signal skew of the data bus.

Here is my code:

**************************************************************************************************** // Data muxes always @* case (1'b1) (MPEGhostActive) : begin // MPEG host port (addr decode of fcs1) fd_mux_out = mpeg_hd; end (fcs2) : begin //IDE port (fcs2) fd_mux_out = ide_fd; end default : begin // fpga fd_mux_out = fd; end endcase

assign fd = fd_oe ? fd_mux_out : 16'bz; // cpu read

***************************************************************************************************** *These are data buses and thus bi-directional - code not shown.

I tried to control the timing in the ucf by using FROM and TO in the following manner:

****************************************************************************************************** INST "ide_fd" TNM = "ide_data_lines"; INST "fd" TNM = "cpu_data_lines"; INST "mpeg_hd" TNM = "mpeg_data_lines"; TIMESPEC "TS_FD2IDE" = FROM "cpu_data_lines" TO "ide_data_lines" 10; TIMESPEC "TS_IDE2FD" = FROM "ide_data_lines" TO "cpu_data_lines" 10; TIMESPEC "TS_FD2MPEG" = FROM "cpu_data_lines" TO "mpeg_data_lines" 10; TIMESPEC "TS_MPEG2FD" = FROM "mpeg_data_lines" TO "cpu_data_lines" 10; *****************************************************************************************************

Unfortunately the timing does not change wether I use the TIMESPEC constraint or not; I just get a warning that "timing was not met" if I use the constraint. Is there a constraint that will force the implementation to meet timing? Signal to signal skew is more important to me than propogation delay but these signals are asynchronous and I could not find a constraint that meets that need - all the skew constraints seem to involve a clock. The way I would implement this in hardware would be to make all the signal traces the same length; is there a similar constraint I can use in FPGA design?

Thanks, Derek

Reply to
soxmax
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I'm not a verilog person, but it looks like you're implementing a combinatorial mux on the data output. AFAIK, you cannot get closure using the timing constraints if the FPGA output is driven by combinatorial logic instead of registers.

Using output registers after the mux allows the output registers to be located in the IOB (I/O Block) at the pin. With a low-skew clock driving the IOB FFs, the skew will be quite low - the sum of the global clock skew to the IOB FFs + the variation in tCKL of the IOB FFs.

Without the register, the complete combinatorial delay for all 16 signals needs to be considered, which is more than the tool can do. The tool has to consider the min/max delays of all of the elements - CLBs and routing - in the path.

Urb

Reply to
Paul Urbanus

You are attempting to do asynchronous design in a synchronous design flow,

By that, I mean, you may bus signals together, and you may register them by having them arrive at flip flops, clocked from the global clock resource.

Then timing constraints will be applied, and all bussed signals will be routed such that they arrive in time to be registered in the flip flops at the rising lock edge.

You do not have to worry about how the routing is done (the tools take care of that for you).

Having signals leave a register, and arrive at another register (after passing through logic, or arithmetic operations) is the basis of synchronous design.

Without registers and clocks, what you want to do is unsupported (asynchronous design in a part designed for synchronous implementation).

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as opposed to:

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(which is unsupported by FPGA design flows)

Austin

Reply to
austin

Derek,

The short answer is you are not supposed to do an asynchronous design in a FPGA. Nothing good will come out.

/Mikhail

Reply to
MM

I wouldn't say that doing an asynchronous design is unsupported in the part. It's the application of the timing constraints to an asynchronous portion the design which is unsupported.

As with all designs, understanding the capabilities of the devices being used along with the performance needs of the final design will lead one to a series of decisions which will insure that all requirements are met.

Urb

Reply to
Paul Urbanus

Paul,

You can hand place and route an asynchronous design using FPGA_Editor, but I do not recommend this. From Xilinx point of view, we do not support asynchronous design.

If you called, and entered a case, and had a problem with an asynchronous design, we would say "don't do that."

Austin

Reply to
austin

Urb, Your typo is telling. Xilinx won't insure you, no matter you ensure your design will work! ;-) Best, Syms.

Reply to
Symon

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