I'll shortly be starting a design in a Zynq FPGA using Vivado. I'm confident that I will be able to use VHDL to create the design, partly because it isn't outside my comfort zone, and partly because there are many app notes/tutorials /books etc on that subject. Timing constraints are a different issue, mainly because they seem to be relatively neglected and un-glamorous.
What I would really like are some examples of "good practice", i.e. small self-contained examples using timing constraints, documenting what is necessary and what is sufficient, and why. I emphasise "small and self-contained" since at this stage I'm not interested in all the arcane possibilities of the constraint languages, merely the common cases with their boundaries. In the software community such things have been given the somewhat fancy name of "design patterns", but it is a valuable concept.
So, I'd be grateful for pointers to references that you found useful when you were learning how to use constraints effectively.
Background is that the logic design will be conventional, with patterns based around * blocks containing FSMs in the form of one VHDL process for the combinatorial logic plus another VHDL process for the registers * two (or more!) clock domains, some with period X, some period 8X (i.e. a nice simple integer relationship) * re-synchronisation across those domain boundaries, using predefined standard Xilinx FPGA primitives * external i/o timing is, perhaps surprisingly, "don't care"; I'll resynchronise inputs myself, and will accept whatever the outputs provide * and I'm presuming that the PLPS interface will be "dealt with" by Vivado without my intervention
So, I'd be grateful for pointers to references that you found useful when you were learning how to use constraints effectively.