Timing Constraint Question

I am working with an EDK design that utilizes an MPMC2 core. There are several clocks associated with this core. All of the clocks are created using DCM's and inverters. I am failing timing b/c cross- clock domain paths are being analyzed and are failing.

My first question is: Should these paths be analyzed for this core? I didn't see any info in the documentation. I know the calibration routine/architecture is supposed to take care of finding the sweet spot to sample data so a TIG should apply for that logic. But I am not certain if every cross-domain path in the core is a TIG.

Second question: If all the paths are indeed TIG's, then is there an easy way to make the constraints? The only timing constraint currently implemented is the input clock to the FPGA that is fed to the DCM chain. Then all other clocks constraints are automatically determined by the tools. Is there a similar feature where I can tell the tools to apply TIG constraints to certain DCM-derived clock paths?

Thanks!

You could TIG the outputs by using:

NET dcm_clock_output_name TIG;

But then you'd have NO timing constraints for that clock at all. Not what you're looking for. One way of handling the cross-domain clocking is to specify a timing constraint for the cross-clock-domain.

Here's an example of this:

NET clk_100MHz TNM = ffs_100; NET clk_200MHz TNM = ffs_200; TIMESPEC TS_100_to_200 = FROM ffs_100 TO ffs_200 10 ns;

This is an example from a MPMC2 design I was working on. It states that where the 100MHz clock meets the 200MHz clock, only worry about meeting 100MHz timing. This design had a MPMC2 core running at 200MHz for DDR2 memory, but the rest of the logic was running at 100MHz. This includes the PPC405s, the ports on the MPMC2, and all of the other logic inside.

One item to note is that this will probably not work if you have CDMAC on the MPMC2. From reading through Xilinx's website, it was stated that the CDMAC in v1.8 did not have enough buffering to handle cross- clock domain timing in its logic. Therefore the MPMC2 core could not running faster than 150MHz. I did get a build together with a 100MHz CDMAC and a 200MHz MPMC2, but did not perform any testing on it.

-- Mike