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timing closure

Hi everyone,

I know the subject is a bit broad, but I'm having issues in achieving timing closure and I'm trying to add timing constraints but a bit randomly...

Any pointer to a good source for a more methodical approach? Thanks a lot,

Al

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Reply to
alb
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If you only have one clock frequency, here is a decent starting point:

Synplify has an option to set a default clock frequency and another to appl y the clock period to all unconstrained IO.

If you have any IO that need tighter constraints than one clock period, you will need to set those up in the constraints manager.

Microsemi also has a good online tutorial for setting up constraints for so urce-synchronous interfaces using virtual clocks.

I prefer to set timing constraints in synthesis so that they are available for both Synplify and Designer. I do not use the Libero front end, only Syn plify and Designer.

If you can avoid them, do not use multi-cycle or false path constraints. Th ey are very difficult to verify without much more expensive tools. It is wa y too easy to relax the timing on unintended paths with these constraints, and unless you hit just the right conditions in a post-P&R simulation, you' ll never know it (until wierd stuff starts happening in the lab or in the f ield).

Hope this helps,

Andy

Reply to
jonesandy

I'm assuming that a system clock and a divided-by-two clock with an internal PLL are still synchronous under all conditions.

So far I'm using SDC files to setup constraints and let Synplify check the constraint file. But I'll explore the constraints manager...

I'm actually looking up the documentation for the 'SCOPE' tool, even though I think I will convert it to SDC once everything is ruled out. I prefer to have physical constraints and timing constraints separate.

I use ModelSim, Synplify and Designer separately. I find the Libero front-end is most of the time in my way... I believe that setting the time constraints during synthesis allows you to have more control on the overall margin that can be taken away during P&R.

I do not particularly like false paths either, especially because it would mean extra efforts to exclude them from verification as well...

Reply to
alb

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