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Timing Behaviour PPC <-> Peripheral Communication Virtex 2 Pro

Hi,

I've designed a PowerPC C++ Application (as standalone configuration) that communicates with an custom peripheral. The custom peripheral, simply counts up a std_logic_vector until it reaches the decimal value 100. This increment is done every clock cycle, the design is made up as an FSM.

Now I send a start signal to the peripheral, the peripheral starts counting. The PowerPC now waits for the peripheral, that sends a "ready" signal, indicating that it puts the first increment to the output register.

Now I want to read every clock cycle from this output register, so that the powerPC gets something like (1,2,3...,100) as input from the peripheral.

Therefore the PowerPC waits for the ready signal and then continously reads the output register.

Unfortunately, all I get as an input from the peripheral is the last value of the counting :(

The peripheral is connected via the OPB bus to the PowerPC, I've learned that this Bus runs at 100 Mhz when configuring the PowerPC to run at 300 Mhz. The clock of the peripheral is connected to the sys_clk_s.

I expect that the PowerPC reads data much faster from the Bus than the peripheral writes them onto the bus. I even build up a clock divider, slowing down the peripheral to sys_clk_s/4 but all I get is the last value.

What is missing in my configuration or do you have an assumption what I am doing wrong?

Any help is highly appreciated, regards Peter

Reply to
Peter Kampmann
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Hmm, I've just read that a read operation on the OPB Bus costs 3 clock cycles, while a read operation costs 4 clock cycles. So my try to get, the output of my peripheral every clock cycle without having to stop the device till the data is read seems not to be able to work...

Or does anybody know something different?

Regards, Peter

Peter Kampmann schrieb:

Reply to
Peter Kampmann

Another remark: If I am using the mentioned clock divider, which shoud slow down my own designed Processes to 25 Mhz, assuming that the OPB runs at 100 Mhz, I should get clock-wise signal outputs in regard to the 25 Mhz clock. The read and write processes are clocked by the BusIP_Clk, so they are running at 100 Mhz.

In the following, I'm posting my test code, perhaps then it is easier to understand what I mean :)

--USER logic implementation added here

my_rst

if(start = '1') then

ctrlState the output of my peripheral every clock cycle without having to stop

Reply to
Peter Kampmann

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