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Timing and synthesis problem+xilinx

Hello, I am using virtex 2 pro for a design of mine. When i am implementing the synethesized edf using ISE it is giving hold time violation on input clock for any frequency given during synthesis. I have given the clock to usaual IBUFG followed by BUFG but its giving delay..i guess so... How can i eleminate this problem?

I have been integrating IP cores but the problem is some of the IP core works fine but when i do minor change on some other module and synthesize....the working IP stop working.... There is no resource problem as i am using only 20% of it and also my clock speeed is 20 MHZ. Can some one point where may be the problem ?

Thanks and regards Williams

Reply to
williams
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Hold time violations that I've seen have generally been due to non-global clock routing resources being used - perhaps it would be worth looking at the design in fpga_editor and checking that the design has been implemented as you expect?

Otherwise, static timing analysis might tell you something about the path - could you post a small section of a signal for which it's failing?

The other indication that something's not quite right is the minor changes causing problems - again, I've seen this in designs that aren't purely synchronous, or in the case where local routing has been used. It indicates that when you resynthesise/map/par, the placement of the logic changes, and that the resulting placement is breaking the design. This would indicate insufficient constraints, constraint violations, or asynch. logic.

Jeremy

Reply to
Jeremy Stringer

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