Hi all, I have the following question, this is my program,
`timescale 1ns / 1ps module oscdiv10(in,out); input in; output out; reg out; reg [3:0] cnt; always @ (in) begin cnt=cnt+1; if (cnt ==9) begin cnt = 0; out = !out; end end endmodule
I have checked this program on the xilinx ISE and it seems to synthesise. Can someone explain what is the .timescale directive and where I can find its help screen (I tried the help from the ISE, but this simply opens my browser somewhere on the xilinx website, and there is no help for it there. Secondly, since I am using blocking assignments, what does it actually mean, will I have propagation delay issues or what? Thirdly, can someone write a short test bench to simulate this on the ISE (shouldn't be too difficult with just one input and one output) and lastly, can someone explain how I can implement this program with a schematic instead of hdl, my problem is what logic devices correspons to 'always' and also to 'if/else'? thanks.