timing?

Hi all, I have the following question, this is my program,

`timescale 1ns / 1ps module oscdiv10(in,out); input in; output out; reg out; reg [3:0] cnt; always @ (in) begin cnt=cnt+1; if (cnt ==9) begin cnt = 0; out = !out; end end endmodule

I have checked this program on the xilinx ISE and it seems to synthesise. Can someone explain what is the .timescale directive and where I can find its help screen (I tried the help from the ISE, but this simply opens my browser somewhere on the xilinx website, and there is no help for it there. Secondly, since I am using blocking assignments, what does it actually mean, will I have propagation delay issues or what? Thirdly, can someone write a short test bench to simulate this on the ISE (shouldn't be too difficult with just one input and one output) and lastly, can someone explain how I can implement this program with a schematic instead of hdl, my problem is what logic devices correspons to 'always' and also to 'if/else'? thanks.

Reply to
<223>
Loading thread data ...

What you need is a good beginners book on Digital Logic Design and another one on Verilog

How will you ever learn if you don't at least try and figure out the answers to your questions yourself?

Reply to
Rob

You won't get what you are expecting without a synchronous block.

Can someone explain what is the .timescale

`timescale /

This is a simulation setting that has no effect on your design.

and where I can find its help screen

formatting link

Use only modelsim and your editor until the design sims ok.

"
Reply to
Mike Treseler

This again?

You didn't use the advice from the last post. Your 'always @(in)' is NOT going to give you what you want. Always blocks are an ABSOLUTELY fudamental constuct in the Verilog HDL and you need to understand them.

Also, Verilog isn't like a software programming language. You need to understand the hardware you are trying to describe and then code that. When I first started learning this I used to draw my circuit (using flip-flops, logic gate, busses, etc) and then use Verilog to describe the circuit. I'm not saying you need to do that, but you need to a least visualize what you are making.

And on this forum, people will be MUCH more responsive if you try things that are suggested, try to learn on your own, and NOT ask if someone will write code for you (like requesting someone to code a testbench).

"(shouldn't be too difficult with just one input and one output)" You are right. It is not too difficult for someone who has taken the initiative and time to learn how. The resources are out there. You know how to use the Internet apparently, so why not try doing some research?

By the way, are you an engineer? Trying to be an engineer? What is the purpose of this?

On another note, if your input frequency is within tolerance, you can use a DCM in the FPGA to divide the clock for you.

Reply to
motty

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.