Hi, I have a moderately big design (~250K equivalent ASIC gates) in Vertex FPGA. The post place & route simulation in Modelsim takes hours together for simulating about 2-3 ms of input data. This is a time killing step in my product development lifecycle. Moreover if some timing errors occur (evenafter analyzing P&R static timing) more syn-map-par-sim iterations are required with modified timing constraints or higher effort levels etc. There are some recent developments in EDA tools like Mentor Graphics' VStation which cater to problems like I am facing by "actually" simulating on the target hardware. But they are toooooooooo costly (I don't know what makes EDA tool companies to fix such a high price for their products) Is there any alternate way of simulating my design ?
Regards, Nagaraj