"This design element is inferred rather than instantiated" (newbie)

As a complete newbie to Verilog and FPGA's, this statement in Xilinx's documentation has me confused.

How do I instantiate library objects that are "inferred rather than instantiated" in my project using HDL? I can add an instance with a schematic but I don't know what this inference means to include this in my Verilog files.

Thanks!

Reply to
Nevo
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Let me try this again in English... :)

How do I include library parts that are "inferred rather than instantiated" in a project when I'm creating the project in Verilog? For instance, if I want a D4_16E (a 4-bit one-of-sixteen decoder) in my project, how would I do that?

Reply to
Nevo

Do you have a good verilog language reference in print form? If not, you should probably invest in one, as the majority of the online ones are incomplete. I've used this one:

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a couple times.

I think this page:

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will answer your question, but doesn't cover the topic in much depth.

Also, don't post verilog questions in comp.arch.fpga unless the are directly related to synthesis on an FPGA. While most of the people here know verilog and/or VHDL, you should still go to comp.lang.verilog if it's nothing but a simple language question. Some people get very hostile if you post in the wrong group. Most just ignore you.

Reply to
Brian McFarland

You use an HDL template that the synthesizer recognizes. If you Google xst.pdf you will find the templates you need.

--
Ben Jackson AD7GD

http://www.ben.com/
Reply to
Ben Jackson

I would recommend to leave this work to the synthesis tool and write a simple case-statement or an if-then-else-statement.

always @(sel, inp_0, ..., inp_f) begin case (sel)

4'h0 : sig
Reply to
Ralf Hildebrandt

So I should copy and paste the templates from the doc into my verilog file?

-Nevo

Reply to
Nevo

Use "Edit->Language Templates..." in ISE and then right mouse click on the template you want to use and then clicking on "Use in file", which copies it for you.

--
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de
Reply to
Frank Buss

This particular question directly relates to synthesis - so I think it made it to the proper group.

As for the question itself, you need to look at the blocks in the XST documentation, and code a structure that looks like it. Remember, VHDL & Verilog are modelling languages.

You really need to know the characteristics of the hardware block you are targeting in order to code that will infer it. For example, most modern FPGA's have synchronous block RAM's, so you must infer registration on the read data, or you will end up with a bunch of FF's. Some BRAM's require registered addresses, etc.

For example, the multiplier unit in a Spartan 3e has either two 9-bit inputs and a 18-bit output, or two 18-bit inputs, and a 36-bit output. You can munge around a bit with the data widths, but this is essentially the structures. They have a single clock with no reset or clock enable.

In VHDL, the code to infer this would be: Mult: process( Clock ) begin if( rising_edge(Clock) )then Mult_Result

Reply to
radarman

You should observe the structures they are creating and see how they apply to your problem, although you can use them verbatim if you want. The synthesizer doesn't require the same literal text, it's just going to look for patterns (eg an asynchronous, two-port RAM) and figure out how to adapt it to the FPGA's hardware. The XST doc will tell you what sorts of RAM you can get with various combinations of ports, clocking, synchronous vs asynchronous access, etc.

--
Ben Jackson AD7GD

http://www.ben.com/
Reply to
Ben Jackson

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