The IDE interface

bjzhangwn schrieb:

page 374 of the t13 spec/1410D revision 3b ... chapter 10.2.1 "Peripherals reporting support for PIO mode 3 or 4 shall power-up in PIO mode 0, 1 or 2."

as the PIO timings are minimum I would assume worst case ... this is power up in PIO mode 0

I could not find any definition for UDMA you should set the UDMA mode after each power up

bye, Michael

Hi,I now use the pio mode 0 to wrrite the registers in the device ,but the device seem not to recceive the data ,becase I read the data from the register just what I write to .And I think if I set the dmack =E3=80=81ata address and the cs signals crrectly, the device shall response to it when I write to the device ,The device I use is produced by seagate,and the jumpers are set to the 7 and 8 to make it the master device,so I do'nt know why.

bjzhangwn schrieb:

standard PIO-0 is really slow and no miracle ...

- read the spec again

- verify your simulation model, simulate again

- read the spec again

- measure the voltages and timings (with a suitable oscilloscope and logic analyzer)

- read the spec again

- measure and compare voltages and timings in a working application (e.g. a regular pc)

- start from beginning

I think these steps are more than obvious and if nothing of that came across your mind ... uhm ... well - maybe you should do something different

bye, Michael

nse

Make sure you really set them correctly; I find the spec to be very hard to read with respect to their polarity - I eventually got it to work, but several things were not as I first assumed/tried. Try searching on IDE or ATA and the names of various embedded processors -

8051, pic, etc and you will find code various hobbysists have used, which can help to understand how to get basic communication working.

Thanks,the specification I have read many times,the fpga I used is stratix 2,and the signals (dmack,ata addr,diow,dior) sampled by the logic analyzer inside the fpga are crrectly.

bjzhangwn schrieb:

I don't think this FPGA can handle 5V ... I assume you use a level shifter outside the fpga? does the direction switching of the data lines work? are the voltage levels ok?

bye, Michael

They match what you designed them to do, but that doesn't mean they are correct for the IDE interface.

Yes,The fpga can't handle 5v , so I must use the 74lv245 to convert the voltage.Now I have made the fpga work successfully,the problem is that levels of the signals (low effective) are all recognized high effective.I make the assert by high level,so the device don't work.