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The Fifo in xapp258

I'm using the Fifo in Xilinx application note xapp258,and the following problem occurs during Behavioral simulation:

The last value in the queue doesn't read out. The same thing happens if I'm writing only one value to the queue, and sets "read_enable_in" high for one clock cycle: No data out. A burst read on eg. the last elements in the Fifo reads out perfectly fine. The last element is beeing read out.

Is it something I'm doing wrong in simulation? Have anyone had this problem with this Fifo or know a solution to it?

Kjetil Vistnes

Reply to
Kjetil Eriksen Vistnes
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Not sure what the problem with the Xilinx FIFOs is, but check out the free FIFOs available on OpenCores, they are also technology independent and can be used with Altera, Xilinx and any Std. Cell process:

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Regards, rudi ======================================================== ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: ..............::: FPGAs * Full Custom ICs * IP Cores ::: FREE IP Cores ->

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Reply to
Rudolf Usselmann

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