The Effect of Pin Assginment

me.

oscillator) initially.

...

144MHz is not problematic on Virtex2 devices. 108MHz even less.

There are many factors that could contribute to your problem.

First would be how you might be implementing your logic. You can trash performance very rapidly by not taking the right approach. For example, multipliers can do 180Mhz, but only if you place your logic taking into consideration routing and use the registerd option.

Second, yes, pin assignment or, more appropriately, floorplanning, has to be an integral part of the project. This isn't software, even though it might look like it. You have to put the time and effort into the initial planning stage in order to ensure success. Here, experience is invaluable. The tools are not going to save you from bad planning or the complete lack thereof.

If your floorplanning is pretty much set in stone (due to your pin assignments) you can try two approaches to getting more performance.

1- Evaluate your logic to see if you can improve the way modules are implemented. You might add FF's in order to allow signals to move from stage to stage and meet timing. 2- Spend more money and move up to a faster speed grade.

Without real details as to your implementation, it is very difficult to offer much more than the above. Oh, yes, "3" would be to hire a capable consultant to fix the problem for you. I am not one, so I can say this without ulterior motives.

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

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> So I reduced the clock period to 108Mhz and redo the P&R for A,B,C,D. This
time FPGA B&E passed. But A&C still failed. I had to reduce 2 Processing
Units for A&C to make them running at 108MHz.
>
> I am quite new to FPGA and have no idea that why I get such strange
results. Please help me and drop me some advice to solve this problem.
>
> Thanks a lot.

Thanks Martin for the valuable advice.

Actually I already made some improvements to the design by reducing Level_Of_Logic, adding FFs and giving some attributes.

Since all the 5 FPGAs shares the same design and some of them can run at a higher frequency, I think floorplanning is a better choice to meet the timing requirement.

For the current project, No manual floorplanning is done. After adding those VHDL files and UCF files, I just let ISE to run automatically.

Frankly speaking, I know nothing about floorplanning. Could anyone recommend any book/tutorial on this topic?

I think you should start with timing simulation rather than floorplanning.

/Mikhail

automatically.

recommend any book/tutorial on this topic?

Hi Mikhail,

But timing simulation will not bring any improvement for timing closure.

It will not bring improvements in itself, but it will hopefully show where and why your design fails to meet your timing requirements and as a result you might be able to fix the problem much faster and cheaper.

/Mikhail

automatically.

any book/tutorial on this topic?

Try to remove pin loc in your UCF, keep the clock/others constraints and let the SW assign the pins for you, see how fast you can go? From the result you may learn something...

Thanks Marlboro,

I did what you recommended and find FPGA A reaches timing closure with the automatic pin assignment.

Good lesson for me.

But how can i minimize the effect of pin assignment? I think i should do floorplanning but i just don't know where to start.

can you recommend me some documents about floorplanning?

Thanks a lot.

I wrote this tutorial about 8 years ago, so it describes tools that don't exist on chips that are not available. Nevertheless, I think it still has enough info and comparison of effort to results, that I haven't taken the page down:

The underlying constraint system and the make up of slices in todays FPGAs is quite similar to what I used for these examples.

Final chips are displayed here:

and the last 5 designs show what can be achieved if one is really persistent.

Philip

Philip Freidin Fliptronics

Take a step back and study the internal structure of the FPGA you are using. Become familiar with the logic resources, connectivity, routing, IOB structure and features, etc. Use FPGA Editor to look inside. Try to understand what it takes to have a signal from a selected I/O pad reach a multiplier or a FF or block ram. Then your I/O assignment choices might come into context.

You might very well find out that only a few of your I/O's are compromised. If you have, for example, a source-synchronous bus comming into the FPGA through less-than-ideal channels, you might be able to carefully add a few reclocking stages to get the signals where they need to go and not have timing problems.

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

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where
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"Ying Hu"  wrote in message
news:ee88431.6@webx.sUN8CHnE...
> Thanks Marlboro,
>
> I did what you recommended and find FPGA A reaches timing closure with the
automatic pin assignment.
>
> Good lesson for me.
>
> But how can i minimize the effect of pin assignment? I think i should do
floorplanning but i just don't know where to start.
>
> can you recommend me some documents about floorplanning?
>
> Thanks a lot.