Testbenching and verification

Hi All,

I am using Quartus and I have acess to Modelsim, and I have been working on a project that is RF based containing lots of filters and other demodulation elements. As I have been going along writing each filter etc, I have been testing it by downloading the finished code to my board and then looking at the output of a filter etc on a spectrum analyser and deciding (subjectively) if it looks right or not. I dont feel this is the right way to go however and I wanted some advise on how you would do test benching on such a project. I have little experience here so I am sure that any advise would be helpful.

I have seen examples using all the testbench directives such as $DISPLAY etc, but I dont think that Quartus likes these directives being in its final code. Also I have writted simulation models for Matlab to confirm the concepts before I write the verilog modules, so if there was someway of comparing a Matlab module to a Verilog module then that would be fantastic.

If anyone could give any advise then that would be most appreciated.

Regards,

Paul Solomon

Reply to
Paul Solomon
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Reply to
Andy Peters

Well, I think you should forget about simulating with such testbenches in Quartus. Quartus does not support file i/o and other things you need to do in simulation with a testbench. You said you have access to ModelSim, that's great! There is a toolbox in Matlab that makes a bridge between ModelSim and Matlab (I think it is called "Link for ModelSim"). Write your testbench in Modelsim and call needed functions in Matlab. You can read the docs in the mathsoft webpage. Consider doing the whole thing first in RTL (i.e. before the synthesize). In many occasions you don't need to such a complex simulation for the post-place and route gate-level models of your design if you have done a good job in simulating the RTL version and have followed a good design practice. All you'd need to do in the gait level would be to run a different testbench to catch timing problems and such. Personally, I like those DSP in FPGA designs very much. Well, wish you good luck :)

Reply to
Arash Salarian

Arash is correct that the Quartus built-in simulator doesn't support the file I/O you'll need to easily compare to Matlab, so you are better off using the ModelSim simulator.

I assume your Matlab flow looks like:

Filter input file -> Read filter inputs -> Filter -> Write Filter Outputs to File

You can perform a simular flow in ModelSim with these steps:

1) Compile the design in Quartus

2) Select Modelsim (Verilog) as the simulation tool

3) Generate EDA Simulation Netlist

4) Design a testbench (similar to the Matlab flow) that instantiates this netlist in Modelsim:

[Read Filter Inputs] => use fopen, fscanf, fclose commands

Pass these filter inputs into the netlist (which is presumably the filter)

Print the outputs to a file using the fopen, fprintf, fclose commands

5) Run the testbench in Modelsim

6) Compare the output of the Matlab simulation with the output of the Modelsim simulation. If you got the format exactly the same, and you expect exactly equivalent output, you could use the diff command on the files. If you expect slight round-off etc. differences and just want to check the filter gives the correct spectral properties, you could read the filter output into Matlab now and Fourier transform it etc. to see if it is doing what you want.

Hope this helps.

Vaughn

Altera

[v b e t z (at) altera.com]
Reply to
Vaughn Betz

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