Hi All,
I am using Quartus and I have acess to Modelsim, and I have been working on a project that is RF based containing lots of filters and other demodulation elements. As I have been going along writing each filter etc, I have been testing it by downloading the finished code to my board and then looking at the output of a filter etc on a spectrum analyser and deciding (subjectively) if it looks right or not. I dont feel this is the right way to go however and I wanted some advise on how you would do test benching on such a project. I have little experience here so I am sure that any advise would be helpful.
I have seen examples using all the testbench directives such as $DISPLAY etc, but I dont think that Quartus likes these directives being in its final code. Also I have writted simulation models for Matlab to confirm the concepts before I write the verilog modules, so if there was someway of comparing a Matlab module to a Verilog module then that would be fantastic.
If anyone could give any advise then that would be most appreciated.
Regards,
Paul Solomon