I'm not sure if this is VHDL or Modelsim issue (other than operator issue), so I'm posting in both groups. It looks like too simple a case to ask someone online, but I've been scratching my head too long on this. I'm relatively new to VHDL (and Modelsim as well).
In a testbench, I'm doing a simple signal generation :
- assert 'sig1' at a rising edge of a free running clock at some point
- deassert 'sig1' at the next rising edge
- and on the 3rd edge, do some checking, and so on...
However, the simlation waveform shows that 'sig1' is asserted from 2nd to 3rd clock edge, instead of being asserted from 1st to 2nd edge.
What am I doing wrong? I've included both snippets from the testbench and the debug output. I expected 'sig1' asserted from 314 to 318ns. Simulation waveform shows assertion from 318 to 322 ns instead. Any help would be appreciated.
# ---------------- in a test bench ------------------- # Wait for a rising edge, and bring 'sig1' high wait until rising_edge(clk); write (L, string'("1st rising edge : " & image(now))); writeline (output, L); sig1